公开(公告)号：US20250054916A1

公开(公告)日：2025-02-13

申请号：US18931874

申请日：2024-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimin CHOI ,  Jeonil LEE ,  Jongmin LEE ,  Juik LEE

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/42 ,  H01L23/48

Abstract: A thermal pad of a semiconductor chip, a semiconductor chip including the thermal pad, and a method of manufacturing the semiconductor chip, the thermal pad including a thermal core in a trench at a lower surface of a semiconductor substrate, the thermal core being configured to receive heat generated from a through silicon via (TSV) vertically extending through the semiconductor substrate; a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate, the thermal head being configured to dissipate the heat in the thermal core; a first insulation layer between an inner surface of the trench and the thermal core; and a second insulation layer between the first insulation layer and the thermal core.

公开(公告)号：US20230178634A1

公开(公告)日：2023-06-08

申请号：US18072784

申请日：2022-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil LEE ,  Gyuhyun KIL ,  Doosan BACK ,  Chansic YOON ,  Junghoon HAN

IPC: H01L29/66 ,  H10B12/00 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/6656 ,  H01L27/10897 ,  H01L27/10894 ,  H01L29/7833 ,  H01L29/6659 ,  H01L29/42364 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10823

Abstract: A semiconductor device includes a substrate, a gate dielectric layer on the substrate, the gate dielectric layer including a recess at a side surface thereof, a gate electrode structure on the gate dielectric layer, a gate capping layer on the gate electrode structure, and a spacer structure on the substrate and covering side surfaces of the gate dielectric layer, the gate electrode structure, and the gate capping layer, the spacer structure including a first spacer, a second spacer on the first spacer and covering the recess, and a third spacer on the second spacer, the second spacer and the third spacer including silicon nitride.

公开(公告)号：US20250120072A1

公开(公告)日：2025-04-10

申请号：US18829537

申请日：2024-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seryeun YANG ,  Jinwoo HAN ,  Jeonil LEE

IPC: H10B12/00 ,  H01L25/065 ,  H10B80/00

Abstract: A memory device includes a peripheral circuit layer including a peripheral circuit region. A cell layer is arranged at a different vertical level from the peripheral circuit layer and includes a cell region. A core layer is arranged between the peripheral circuit layer and the cell layer and is electrically connected to the peripheral circuit region and the cell region. The cell region includes a plurality of cell banks each including a memory component. The core circuit region includes a plurality of core banks arranged at positions at least partially vertically overlapping the plurality of cell banks, respectively. Each of the plurality of core banks includes a core circuit.

公开(公告)号：US20250089236A1

公开(公告)日：2025-03-13

申请号：US18954927

申请日：2024-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil LEE ,  Youngjun KIM ,  Jinbum KIM

IPC: H10B12/00

Abstract: A semiconductor device including an active pattern; a gate structure connected to the active pattern; a bit line structure connected to the active pattern; a buried contact connected to the active pattern; a contact pattern covering the buried contact; a landing pad connected to the contact pattern; and a capacitor structure connected to the landing pad, wherein the buried contact includes a first growth portion and a second growth portion spaced apart from each other, and the landing pad includes an interposition portion between the first growth portion and the second growth portion.

公开(公告)号：US20230078980A1

公开(公告)日：2023-03-16

申请号：US17696989

申请日：2022-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jimin CHOI ,  Jeonil LEE ,  Jongmin LEE ,  Juik LEE

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/42 ,  H01L23/48

Abstract: A thermal pad of a semiconductor chip, a semiconductor chip including the thermal pad, and a method of manufacturing the semiconductor chip, the thermal pad including a thermal core in a trench at a lower surface of a semiconductor substrate, the thermal core being configured to receive heat generated from a through silicon via (TSV) vertically extending through the semiconductor substrate; a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate, the thermal head being configured to dissipate the heat in the thermal core; a first insulation layer between an inner surface of the trench and the thermal core; and a second insulation layer between the first insulation layer and the thermal core.

公开(公告)号：US20250053322A1

公开(公告)日：2025-02-13

申请号：US18650412

申请日：2024-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil LEE ,  Jinwoo HAN ,  Seryeun YANG

IPC: G06F3/06

Abstract: There is provided a memory device including a processing-in-memory (PIM) dynamic random access memory (DRAM) die(s) and PIM-high bandwidth memory (HBM) devices. The memory device includes a core peripheral circuit structure including a bank core circuit including a row decoder and a sense amplifier of each of a plurality of banks, and a cell array structure disposed on the core peripheral circuit structure. The bank core circuit includes a plurality of sub core circuits correspondingly connected to the plurality of sub cell blocks, respectively. Each of the plurality of sub core circuits includes a sense amplifier segmented to be connected to a corresponding sub cell block, and a processing element connected to the segmented sense amplifier and configured to perform a logical operation on an operand that is data loaded into the segmented sense amplifier.

公开(公告)号：US20230051597A1

公开(公告)日：2023-02-16

申请号：US17579919

申请日：2022-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil LEE ,  Youngjun KIM ,  Jinbum KIM

IPC: H01L27/108

Abstract: A semiconductor device including an active pattern; a gate structure connected to the active pattern; a bit line structure connected to the active pattern; a buried contact connected to the active pattern; a contact pattern covering the buried contact; a landing pad connected to the contact pattern; and a capacitor structure connected to the landing pad, wherein the buried contact includes a first growth portion and a second growth portion spaced apart from each other, and the landing pad includes an interposition portion between the first growth portion and the second growth portion.

公开(公告)号：US20200286732A1

公开(公告)日：2020-09-10

申请号：US16807702

申请日：2020-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Janghee LEE ,  Seunggeol NAM ,  Hyeonjin SHIN ,  Hyunseok LIM ,  Alum JUNG ,  Kyung-Eun BYUN ,  Jeonil LEE ,  Yeonchoo CHO

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/26

Abstract: Provided are a method of pre-treating a substrate and a method of directly forming graphene by using the method of pre-treating the substrate. In the method of pre-treating the substrate in the method of directly forming graphene, according to an embodiment, the substrate is pre-treated by using a pre-treatment gas including at least a carbon source and hydrogen. The method of directly forming graphene includes a process of pre-treating a substrate and a process of directly growing graphene on the substrate that is pre-treated. The process of pre-treating the substrate is performed according to the method of pre-treating the substrate.

公开(公告)号：US20240322048A1

公开(公告)日：2024-09-26

申请号：US18606081

申请日：2024-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Jeonil LEE ,  Minhee CHO ,  Daweon HA

IPC: H01L29/792 ,  H10B12/00

CPC classification number: H01L29/7926 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488

Abstract: Provided is an integrated circuit device including a source line extending in a first horizontal direction on a substrate, a channel layer extending in a vertical direction, disposed on the source line, and having a first sidewall and a second sidewall, a trapping layer on the first sidewall of the channel layer and including an oxide semiconductor, a word line on at least one sidewall of the trapping layer and extending in a second horizontal direction crossing the first horizontal direction, a gate insulation layer between the at least one sidewall of the trapping layer and the word line, and a bit line electrically connected to the channel layer and extending in the first horizontal direction, wherein the channel layer has a first bandgap energy, and the trapping layer has a second bandgap energy that is greater than the first bandgap energy.

公开(公告)号：US20230389290A1

公开(公告)日：2023-11-30

申请号：US18200135

申请日：2023-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil LEE ,  Kyunghwan LEE ,  Min Hee CHO

IPC: H10B12/00 ,  H10B53/10 ,  H10B53/30 ,  H01L29/08

CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/485 ,  H10B53/10 ,  H10B53/30 ,  H01L29/0847

Abstract: A semiconductor device includes a first single crystal semiconductor pattern including a first source/drain region, a second source/drain region, and a first vertical channel region between the first source/drain region and the second source/drain region, the second source/drain region being at a higher level than the first source/drain region; a first gate electrode facing a first side surface of the first single crystal semiconductor pattern; a first gate dielectric layer, the first gate dielectric layer including a portion between the first single crystal semiconductor pattern and the first gate electrode; and a complementary structure in contact with a second side surface of the first single crystal semiconductor pattern, wherein the complementary structure includes an oxide semiconductor layer.