公开(公告)号：DE19842883A1

公开(公告)日：2000-03-30

申请号：DE19842883

申请日：1998-09-18

Applicant: SIEMENS AG

Inventor： REISINGER HANS ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  STENGL REINHARD ,  LEHMANN VOLKER ,  LANGE GERRIT ,  WENDT HERMANN

IPC: H01L21/8247 ,  H01L21/8229 ,  H01L27/102 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: An electrically programmable nonvolatile memory cell structure has address lines (70) extending along side walls of trenches (30). An Independent claim is also included for production of an electrically programmable nonvolatile memory cell structure by: (a) forming insulation-filled parallel isolation trenches in a first conductivity type semiconductor substrate (25); (b) forming parallel trenches (30) perpendicular to the isolation trenches to leave ribs (35) which subdivide individual substrate regions (45); (c) coating the trench side walls (75) with an interlayer (65) and then second conductivity type doped address lines (70); and (d) annealing the substrate so that dopant diffuses from the address lines (70) through the interlayer (65) into the substrate regions (45) to form second conductivity type doped regions (55) with a direct junction (60) with the first conductivity type. Preferred Features: The address lines (70) consist of doped polysilicon with a dopant content of 10 -10 cm .

公开(公告)号：DE19631147C2

公开(公告)日：2001-08-09

申请号：DE19631147

申请日：1996-08-01

Applicant: SIEMENS AG

Inventor： REISINGER HANS ,  STENGL REINHARD ,  GRUENING ULRIKE ,  WENDT HERMANN ,  WILLER JOSEF ,  LEHMANN VOLKER ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  KRAUTSCHNEIDER WOLFGANG ,  HOFMANN FRANZ

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

Abstract: The invention concerns a non-volatile write-once storage cell comprising a MOS transistor which, as gate dielectric, has a triple dielectric layer consisting of a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53). The first silicon oxide layer (51) and the second silicon oxide layer (53) are each at least 3 nm thick. The storage cell is not erasable and can hold data for a period of more than 1000 years.

公开(公告)号：DE19914496A1

公开(公告)日：2000-10-05

申请号：DE19914496

申请日：1999-03-30

Applicant: SIEMENS AG

Inventor： WILLER JOSEF ,  REISINGER HANS ,  SCHLOESSER TILL ,  STENGL REINHARD

IPC: H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

Abstract: A memory cell structure comprises a contact (K) within a substrate (S) for connecting a capacitor and a MOS transistor on opposite substrate surfaces (O1, O2). A memory cell structure comprises a MOS transistor connected to a bit line (B) on one substrate surface (O1), a capacitor on the opposite substrate surface (O2) and a contact (K) in the substrate (S) for connecting the capacitor with the MOS transistor. An Independent claim is also included for production of the above memory cell structure.

公开(公告)号：DE19842882A1

公开(公告)日：2000-03-30

申请号：DE19842882

申请日：1998-09-18

Applicant: SIEMENS AG

Inventor： REISINGER HANS ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  STENGL REINHARD ,  LEHMANN VOLKER ,  LANGE GERRIT ,  WENDT HERMANN

IPC: H01L21/225 ,  H01L21/768 ,  H01L21/8239 ,  H01L27/105 ,  H01L21/329

Abstract: Doped region production involves thermally diffusing dopant from a semiconductor layer through an insulating interlayer (40, 70) and then making the interlayer (40, 70) electrically conductive. A doped region is produced by: (a) successively applying an insulating interlayer (40, 70) and a first conductivity type doped semiconductor layer onto a semiconductor substrate (15); (b) annealing the substrate so that dopant diffuses from the semiconductor layer through the interlayer (40, 70) into the substrate to form one or more first conductivity type doped regions (55, 80); and (c) altering the electrical conductivity of the interlayer (40, 70) to produce electrical contact between the doped region (55, 80) and the semiconductor layer. Preferred Features: The interlayer (40, 70) consists of silicon oxide and is made conductive by a voltage or current pulse.

公开(公告)号：DE19821901A1

公开(公告)日：1999-11-25

申请号：DE19821901

申请日：1998-05-15

Applicant: SIEMENS AG

Inventor： REISINGER HANS ,  STENGL REINHARD ,  GRUENING ULRIKE ,  LEHMANN VOLKER ,  WENDT HERMANN ,  WILLER JOSEF ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT

IPC: H01L21/8244 ,  H01L27/11 ,  G11C11/412

Abstract: The circuit includes at least one memory cell arranged in the area of a surface of a semiconductor substrate. The memory cell contains at least two electrically connected invertors (I1, I2) which contain respectively two complementary MOS transistors with a source, a drain and a channel. The channels of the transistors comprise different conductivities. The invertors are arranged vertically to the surface of the semiconductor substrate, whereby the sources, the drains and the channel of the complementary MOS transistors are formed through stacked layers which are arranged in such way, that the complementary MOS transistors are placed on each other.

公开(公告)号：DE19840824C1

公开(公告)日：1999-10-21

申请号：DE19840824

申请日：1998-09-07

Applicant: SIEMENS AG

Inventor： HANEDER THOMAS ,  REISINGER HANS ,  STENGL REINHARD ,  BACHHOFER HARALD ,  WENDT HERMANN ,  HOENLEIN WOLFGANG

IPC: H01L21/8247 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336 ,  H01L27/11 ,  G11C11/412 ,  H01L27/12

Abstract: The invention relates to a ferroelectric transistor suitable for use as a storage element, which between source/drain zones (12) on the surface of a semiconductor substrate (11) has a first gate interlayer (13) and a first gate electrode (14). The first gate interlayer (13) contains at least one ferroelectric layer (132). A second gate interlayer (16) and a second gate electrode (17) are arranged next to the first gate interlayer (13) between the source/drain zones (12) and said second gate interlayer (16) contains a dielectric layer. The first gate electrode (14) and the second gate electrode (17) are connected via a diode structure.

公开(公告)号：DE19860501A1

公开(公告)日：2000-07-06

申请号：DE19860501

申请日：1998-12-28

Applicant: SIEMENS AG

Inventor： LANGE GERRIT ,  FRANOSCH MARTIN ,  STENGL REINHARD ,  HOFMANN FRANZ ,  KRAUTSCHNEIDER WOLFGANG ,  REISINGER HANS ,  SCHLOESSER TILL ,  WILLER JOSEF

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: Capacitor production involves applying a conductive support structure (8') to a structured sequence of alternating conductive layers (61) and sacrificial layers prior to selective sacrificial layer removal. An integrated circuit (IC) capacitor production process comprises: (a) applying a first layer of a first conductive material onto a support; (b) forming a raised structure (5) of the first conductive material or another material on the first layer; (c) producing a layer sequence of alternating first material layers (61) and second material layers, the lowermost layer consisting of material different from that of the raised structure; (d) removing the layer sequence from above the raised structure; (e) structuring the layer sequence and the first layer down to the support to form a layer structure with side walls; (f) covering the layer structure side walls with a support structure (8') of a conductive material, preferably the first material; (g) selectively removing the second material layers; (h) forming a capacitor dielectric (9) on the exposed surfaces of the first material layers (61), the first layer and the support structure (8'); and (i) forming a counter-electrode (10) on the dielectric (9).

公开(公告)号：DE19911150C1

公开(公告)日：2000-04-20

申请号：DE19911150

申请日：1999-03-12

Applicant: SIEMENS AG

Inventor： WENDT HERMANN ,  FRITSCH ELKE ,  STENGL REINHARD ,  HOENLEIN WOLFGANG ,  SCHWARZL SIEGFRIED ,  BEITEL GERHARD

IPC: B81C1/00 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L21/3205 ,  H01L21/8239

Abstract: Microelectronic structure production, comprising physically etching a conductive layer (45) from a substrate (5) such that removed material is transferred onto a layer structure side wall (35), is new. A microelectronic structure production process comprises (a) partially covering a substrate (5) with a layer structure (30) including one or more first conductive layers (15, 20) which extend to the layer structure side wall (35); (b) applying a second conductive layer (45) onto the layer structure and the substrate; and (c) removing the second conductive layer (45) from the substrate by a physical etching process such that the removed material deposits on the layer structure side wall. Preferred Features: The first conductive layer (15, 20) is a barrier and/or bond layer of a titanium nitride/titanium or tantalum nitride/tantalum combination and the second conductive layer (45) consists of Pt. The layer stack (30) is subsequently covered with a dielectric layer of formula ABOx or DOx, where A = one or more of Sr, Bi, Nb, Pb, Zr, La, Li, K, Ca and Ba, B = one or more of Ti, Nb, Ru, Mg, Mn, Zr and Ta, D = Ti or Ta and x = 2 to 12.

公开(公告)号：DE19840238C1

公开(公告)日：2000-03-16

申请号：DE19840238

申请日：1998-09-03

Applicant: SIEMENS AG

Inventor： FRANOSCH MARTIN ,  STENGL REINHARD ,  SCHAEFER HERBERT ,  REISINGER HANS ,  ILG MATTHIAS

IPC: C23C16/24 ,  C23C16/56 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242

Abstract: Chemical vapor deposition (CVD) of a doped silicon layer, uses a process gas which contains disilane in addition to monosilane and dopant gas. A doped silicon layer is produced by CVD of a silicon layer (3) from a process gas containing silane (SiH4), disilane (Si2H6) and a dopant gas and treating at 600 deg C and at 133.32 mbar to atmospheric pressure within the CVD reactor. An Independent claim is also included for a microelectronic structure with a 50-200 nm thick conductive element of doped silicon with

公开(公告)号：DE19821776C1

公开(公告)日：1999-09-30

申请号：DE19821776

申请日：1998-05-14

Applicant: SIEMENS AG

Inventor： LANGE GERRIT ,  FRANOSCH MARTIN ,  LEHMANN VOLKER ,  REISINGER HANS ,  SCHAEFER HERBERT ,  STENGL REINHARD ,  WENDT HERMANN

IPC: H01L21/8242 ,  H01L27/108

Abstract: An IC capacitor is produced by forming a conductive prop (7) in an alternate conductive and sacrificial layer sequence, removing the sacrificial layers and forming a dielectric (9) on the exposed surfaces. A capacitor is produced in an IC by: (a) coating a support (2) with a layer sequence of alternate conductive layers (61) and sacrificial layers; (b) forming an opening in the layer sequence; (c) forming an conductive prop structure (7) in the opening; (d) anisotropically etching the layer sequence to the lateral dimensions of the capacitor; (e) selectively removing the sacrificial layers; (f) forming a capacitor dielectric (9) on the exposed surfaces of the first material layers (61) and the prop structure (7); and (g) forming a counterelectrode (10) on the dielectric surface.