公开(公告)号：JPH10242430A

公开(公告)日：1998-09-11

申请号：JP5912998

申请日：1998-02-25

Applicant: SIEMENS AG

Inventor： FRANOSCH MARTIN DIPL PHYS ,  SCHAEFER HERBERT ,  STENGL REINHARD ,  LANGE GERRIT ,  LEHMANN VOLKER ,  WENDT HERMANN ,  REISINGER HANS DR

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To reduce manufacture cost by alternately forming layer rows which alternately have layers formed of silicon and layers containing germanium on a substrate, forming supporting patterns so that they cover the layer rows, selectively removing the layers containing germanium and forming dielectrics and the like on the surface of the supporting patterns. SOLUTION: An insulating layer 2 is formed on the substrate 1 and the layer strings where the layers 41 formed of silicon and the layers 42 containing germanium are alternately doped are formed on the surface of the insulating layer 2. Layer patterns 4' are formed so that the surface of the insulating layer 2 is exposed by anisotropic etching. The supporting patterns 5 covering the sides and the surfaces of the layer patterns 4' are formed by selective epitaxy. The part of the layers 42 containing germanium is removed by selective etching so that the layers 41 constituted of doped silicon and the supporting patterns remain. Then, the capacitor dielectrics 6 and a counter electrode 7 are formed on the surfaces of the layers 41 formed of doped silicon and the supporting patterns 5.

公开(公告)号：JPH10242429A

公开(公告)日：1998-09-11

申请号：JP5912898

申请日：1998-02-25

Applicant: SIEMENS AG

Inventor： FRANOSCH MARTIN DIPL PHYS ,  HOENLEIN WOLFGANG ,  KLOSE HELMUT ,  LANGE GERRIT ,  LEHMANN VOLKER ,  REISINGER HANS DR ,  SCHAEFER HERBERT ,  STENGL REINHARD ,  WENDT HERMANN ,  WIDMANN DIETRICH

IPC: H01L21/306 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To reduce manufacture cost by alternately forming a silicon layer and a layer containing germanium in a trench on a semiconductor substrate, forming a supporting pattern, removing the layer containing germanium and forming an electrode pattern. SOLUTION: A trench mask 13 is formed on the semiconductor substrate 12 and the trench is formed by etching. A dope region 15, the layer 16 containing germanium, the silicon layer 17 and the layer 18 containing germanium are formed in the trench. Then, a base part is removed and a polysilicon layer 20 becoming the supporting pattern is formed. Then, the upper part of the polysilicon layer 20 is etched back and the layers 16 and 18 containing germanium are removed by selective etching. Then, the electrode pattern 21 is formed. A memory dielectric 22 is formed on the surface of the electrode pattern 21, a counter electrode 23 by the polysilicon layer is formed so that the internal part of the trench is filled and a capacitor is formed. Furthermore, source/drain regions 24 are formed.

公开(公告)号：WO9965063A3

公开(公告)日：2000-03-16

申请号：PCT/DE9901454

申请日：1999-05-12

Applicant: SIEMENS AG ,  REISINGER HANS ,  LEHMANN VOLKER ,  STENGL REINHARD ,  WENDT HERMANN ,  LANGE GERRIT ,  BACHHOFER HARALD ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT

Inventor： REISINGER HANS ,  LEHMANN VOLKER ,  STENGL REINHARD ,  WENDT HERMANN ,  LANGE GERRIT ,  BACHHOFER HARALD ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/1085 ,  H01L27/10805

Abstract: (57) Abstract The invention relates to a DRAM storage capacitor, comprising a dielectric made of silicon nitride and at least two electrodes placed opposite to each other above the dielectric. A material with higher tunnel barrier ( phi beta ) between the Fermi level (F) of the material and the conduction band (L) of the dielectric is used for the electrodes. For said purpose, the appropriate materials are metals such a platinum, tungsten and iridium or silicide. (57) Zusammenfassung Die Erfindung betrifft einen Speicherkondensator für einen DRAM, mit einem aus Siliziumnitrid bestehenden Dielektrikum und mit wenigstens zwei, über das Dielektrikum einander gegenüberliegenden Elektroden. Für die Elektroden wird ein Material mit hoher Tunnelbarriere ( phi beta ) zwischen Fermi-Niveau (F) des Materials und Leitungsband (L) des Dielektrikums verwendet. Geeignete Materialien sind hierfür Metalle wie Platin, Wolfram und Iridium oder Silizide.

Abstract translation: 本发明涉及一种存储电容器用于DRAM，包括由氮化硅的电介质构成的组，和具有至少两个电极在所述电介质彼此相对。 对于使用电介质的材料具有高的隧道势垒（PHI测试版）的材料和导带（L）的费米能级（F）之间的电极。 用于此目的的合适的材料是金属，例如铂，钨，和铱，或硅化物。

公开(公告)号：DE19842682A1

公开(公告)日：2000-04-06

申请号：DE19842682

申请日：1998-09-17

Applicant: SIEMENS AG

Inventor： LANGE GERRIT ,  SCHLOESSER TILL ,  FRANOSCH MARTIN ,  WENDT HERMANN

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L21/283

Abstract: A high-permittivity dielectric (9) type capacitor for mounting in a semiconductor arrangement on a carrier includes a first electrode (61,7) containing a noble metal and a second electrode (10), the capacitor dielectric consisting of a high-permittivity dielectric or ferroelectric material. The first electrode (61,7) has at least two mutually spaced apart laminations (61) arranged mainly parallel to the carrier surface and mechanically and electrically joined to one another via a support structure (7). More specifically, the carrier contains a MOS-transistor, and a contact (3) is connected to the first electrode (6a,7) and joins a source/drain zone (11) of the transistor to the first electrode.

公开(公告)号：DE19842883A1

公开(公告)日：2000-03-30

申请号：DE19842883

申请日：1998-09-18

Applicant: SIEMENS AG

Inventor： REISINGER HANS ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  STENGL REINHARD ,  LEHMANN VOLKER ,  LANGE GERRIT ,  WENDT HERMANN

IPC: H01L21/8247 ,  H01L21/8229 ,  H01L27/102 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: An electrically programmable nonvolatile memory cell structure has address lines (70) extending along side walls of trenches (30). An Independent claim is also included for production of an electrically programmable nonvolatile memory cell structure by: (a) forming insulation-filled parallel isolation trenches in a first conductivity type semiconductor substrate (25); (b) forming parallel trenches (30) perpendicular to the isolation trenches to leave ribs (35) which subdivide individual substrate regions (45); (c) coating the trench side walls (75) with an interlayer (65) and then second conductivity type doped address lines (70); and (d) annealing the substrate so that dopant diffuses from the address lines (70) through the interlayer (65) into the substrate regions (45) to form second conductivity type doped regions (55) with a direct junction (60) with the first conductivity type. Preferred Features: The address lines (70) consist of doped polysilicon with a dopant content of 10 -10 cm .

公开(公告)号：DE19842704A1

公开(公告)日：2000-04-06

申请号：DE19842704

申请日：1998-09-17

Applicant: SIEMENS AG

Inventor： LANGE GERRIT ,  SCHLOESSER TILL

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L21/8239

Abstract: Capacitor production in a semiconductor structure involves producing a lower electrode in the form of horizontal spaced lamellae joined together by a support structure. A capacitor is produced in a semiconductor structure on a support by: (a) forming alternate first and second material layers on the support surface, the first material being selectively etchable with respect to the second material; (b) etching the layer sequence to form a layer structure; (c) covering one side wall of the structure with a first auxiliary structure which is selectively etchable with respect to the second material; (d) covering another side wall of the structure with a second auxiliary structure which mechanically connects the second material layers; (e) applying a filler layer to cover the surrounding support surface up to the upper edge of the layer structure; (f) selectively removing the first material layers and the first auxiliary structure; (g) filling the resulting spaces with a precious metal electrode material to form a first electrode in the form of lamellae (9L) connected by a support structure (9S); (h) selectively removing the second material layers and the second auxiliary structure; (i) applying a conformal capacitor dielectric (10) of high epsilon dielectric or ferroelectric material onto the exposed first electrode surfaces; and (j) producing a second electrode (11) on the capacitor dielectric. An Independent claim is also included for a capacitor produced by the above process.

公开(公告)号：DE19860501A1

公开(公告)日：2000-07-06

申请号：DE19860501

申请日：1998-12-28

Applicant: SIEMENS AG

Inventor： LANGE GERRIT ,  FRANOSCH MARTIN ,  STENGL REINHARD ,  HOFMANN FRANZ ,  KRAUTSCHNEIDER WOLFGANG ,  REISINGER HANS ,  SCHLOESSER TILL ,  WILLER JOSEF

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: Capacitor production involves applying a conductive support structure (8') to a structured sequence of alternating conductive layers (61) and sacrificial layers prior to selective sacrificial layer removal. An integrated circuit (IC) capacitor production process comprises: (a) applying a first layer of a first conductive material onto a support; (b) forming a raised structure (5) of the first conductive material or another material on the first layer; (c) producing a layer sequence of alternating first material layers (61) and second material layers, the lowermost layer consisting of material different from that of the raised structure; (d) removing the layer sequence from above the raised structure; (e) structuring the layer sequence and the first layer down to the support to form a layer structure with side walls; (f) covering the layer structure side walls with a support structure (8') of a conductive material, preferably the first material; (g) selectively removing the second material layers; (h) forming a capacitor dielectric (9) on the exposed surfaces of the first material layers (61), the first layer and the support structure (8'); and (i) forming a counter-electrode (10) on the dielectric (9).

公开(公告)号：DE19821776C1

公开(公告)日：1999-09-30

申请号：DE19821776

申请日：1998-05-14

Applicant: SIEMENS AG

Inventor： LANGE GERRIT ,  FRANOSCH MARTIN ,  LEHMANN VOLKER ,  REISINGER HANS ,  SCHAEFER HERBERT ,  STENGL REINHARD ,  WENDT HERMANN

IPC: H01L21/8242 ,  H01L27/108

Abstract: An IC capacitor is produced by forming a conductive prop (7) in an alternate conductive and sacrificial layer sequence, removing the sacrificial layers and forming a dielectric (9) on the exposed surfaces. A capacitor is produced in an IC by: (a) coating a support (2) with a layer sequence of alternate conductive layers (61) and sacrificial layers; (b) forming an opening in the layer sequence; (c) forming an conductive prop structure (7) in the opening; (d) anisotropically etching the layer sequence to the lateral dimensions of the capacitor; (e) selectively removing the sacrificial layers; (f) forming a capacitor dielectric (9) on the exposed surfaces of the first material layers (61) and the prop structure (7); and (g) forming a counterelectrode (10) on the dielectric surface.

公开(公告)号：DE19820756C1

公开(公告)日：1999-11-11

申请号：DE19820756

申请日：1998-05-08

Applicant: SIEMENS AG

Inventor： LEHMANN VOLKER ,  REISINGER HANS ,  WENDT HERMANN ,  STENGL REINHARD ,  LANGE GERRIT ,  OTTOW STEFAN

IPC: C25F3/12 ,  C25F3/02 ,  H01P1/20 ,  B26F1/26

Abstract: A perforated workpiece, comprising a silicon substrate (1) having a first region (6) with through-pores (4) and a second region (7) with blind pores, is new. An Independent claim is also included for producing a perforated workpiece by electrochemically etching one face (2) of a silicon substrate (1) to form pores (4) of depth less than the substrate thickness, providing the opposite substrate face (3) with a mask layer which exposes first regions (6) of this opposite substrate face, etching the exposed face regions (6) to the bottoms of the pores (4) and then removing the mask layer.

公开(公告)号：DE19842882A1

公开(公告)日：2000-03-30

申请号：DE19842882

申请日：1998-09-18

Applicant: SIEMENS AG

Inventor： REISINGER HANS ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  STENGL REINHARD ,  LEHMANN VOLKER ,  LANGE GERRIT ,  WENDT HERMANN

IPC: H01L21/225 ,  H01L21/768 ,  H01L21/8239 ,  H01L27/105 ,  H01L21/329

Abstract: Doped region production involves thermally diffusing dopant from a semiconductor layer through an insulating interlayer (40, 70) and then making the interlayer (40, 70) electrically conductive. A doped region is produced by: (a) successively applying an insulating interlayer (40, 70) and a first conductivity type doped semiconductor layer onto a semiconductor substrate (15); (b) annealing the substrate so that dopant diffuses from the semiconductor layer through the interlayer (40, 70) into the substrate to form one or more first conductivity type doped regions (55, 80); and (c) altering the electrical conductivity of the interlayer (40, 70) to produce electrical contact between the doped region (55, 80) and the semiconductor layer. Preferred Features: The interlayer (40, 70) consists of silicon oxide and is made conductive by a voltage or current pulse.