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公开(公告)号：JPH11234689A
公开(公告)日：1999-08-27
申请号：JP3089798
申请日：1998-02-13
Applicant: SONY CORP
Inventor： GAMO NAOYASU
Abstract: PROBLEM TO BE SOLVED: To provide the video signal processing circuit that eliminates a pseudo aperture control without deleting vertical aperture control of an object with high luminance and high gradation, and to provide its processing method and the camera system using them. SOLUTION: Detection of a luminance level detection section 30 is a main stream of the processing. Detection of a level difference between adjacent lines in a vertical direction by a vertical direction detection section 29 is also conducted. Even when detection is intermittently conducted by a continuing means consisting of a delay circuit 304, an OR circuit 305, a delay circuit 292 and an OR circuit 294, a detection signal is continuously outputted and a limit period setting circuit 32 sets a limit period to a V aperture control limiter section 28 based on the detection signal.
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公开(公告)号：JP2005033679A
公开(公告)日：2005-02-03
申请号：JP2003272973
申请日：2003-07-10
Inventor： GAMO NAOYASU
Abstract: PROBLEM TO BE SOLVED: To be able to reduce data transfer control load per unit data bus by devising the system structure of a data bus and to be able to reduce power consumption.
SOLUTION: A mobile CPU 10 for a mobile terminal comprises a compression expansion unit 16 for inputting and compressing the moving video information or expanding the moving video information compressed already, a CPU 15 for inputting the moving video information to conduct image processing other than compression and expansion, a data bus 91 for transmitting the moving video information processed by the CPU 15, a data bus 92 for transmitting the moving video information compressed by the compression expansion unit 16, and a bus switching unit 14 for selecting either one of the data bus 91 connected to the CPU 15 or the data bus 92 connected to the compression expansion unit 16. The CPU 10 can employ a configuration in which the data bus 91 for transmitting moving video information processed by the CPU 15 is separated from the data bus 92 for transmitting moving video information compressed by the compression expansion unit 16.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：通过设计数据总线的系统结构，能够减少每单位数据总线的数据传输控制负载，并能够降低功耗。 解决方案：用于移动终端的移动CPU 10包括用于输入和压缩移动视频信息或扩展已经压缩的运动视频信息的压缩扩展单元16，用于输入运动视频信息以执行其他图像处理的CPU 15 压缩和扩展的数据总线91，用于发送由CPU 15处理的运动视频信息的数据总线91，用于发送由压缩扩展单元16压缩的运动视频信息的数据总线92以及总线切换单元14，用于选择 连接到CPU 15的数据总线91或连接到压缩扩展单元16的数据总线92.CPU 10可以采用其中用于将由CPU 15处理的运动视频信息发送的数据总线91与数据分离的配置 总线92，用于发送由压缩扩展单元16压缩的运动视频信息。版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JPH10276348A
公开(公告)日：1998-10-13
申请号：JP8039997
申请日：1997-03-31
Applicant: SONY CORP
Inventor： GAMO NAOYASU
IPC: H04N5/202
Abstract: PROBLEM TO BE SOLVED: To provide the video signal processing circuit that realizes both gradation emphasis in the vicinity of a black level and emphasized S/N functions by means of same signal processing while making the circuit scale small, to provide the camera employing the circuit and to provide the gamma correction method. SOLUTION: The gamma correction circuit is formed to be a ROM table system gamma correction circuit provided with a gamma ROM 11 that generates data of a standard gamma curve characteristic with respect to a received correction object Y signal, with a correction data generating section 12 that generates correction data to correct a characteristic of an area around a black level of a standard gamma curve characteristic and with a subtractor 13 that subtracts the correction data from data of the standard gamma curve characteristic. Then both gradation emphasis in the vicinity of a black level and emphasized S/N functions are realized by means of same signal processing.
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公开(公告)号：JPH06204743A
公开(公告)日：1994-07-22
申请号：JP36217692
申请日：1992-12-28
Applicant: SONY CORP
Inventor： GAMO NAOYASU , KITAZONO SHINICHI , ISHIKAWA FUMIO
IPC: H03B5/12
Abstract: PURPOSE:To obtain an oscillator and mixer in which the number of elements is reduced, the circuit is simplified, the cost is reduced and the size is made small. CONSTITUTION:The oscillator and mixer is provided with a 1st oscillation circuit OSCv, a buffer BUFV having oscillation transistors (TRs) QV1,V2 connecting to a resonance circuit RSNV and a buffer TR connecting to the oscillation TRs and load elements RB1-RB3 and outputting the oscillation signal of a prescribed frequency and with a 2nd oscillation circuit OSCU having oscillation TRs QU1,U2 connecting to a resonance circuit RSN. Collectors of the oscillation TRs QU1,U2 of the 2nd oscillation circuit OSCU are connected to load elements RB1-RB3 of the 1st oscillation circuit OSCV to output the oscillation signal of a prescribed frequency and the load elements RB1-RB3 are used in common by the 1st and 2nd oscillation circuits, then the number of elements is reduced.
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