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公开(公告)号：JPH1023461A
公开(公告)日：1998-01-23
申请号：JP17022996
申请日：1996-06-28
Applicant: SONY CORP
Inventor： GAMO NAOYASU
Abstract: PROBLEM TO BE SOLVED: To reduce the number of signal lines to be laid. SOLUTION: Parallel data latched by latch circuits 14a to 14c are respectively supplied to their lower latch circuits 14b to 14d through respective selector circuits 13b to 13d and the parallel data latched by the lowermost latch circuit 14d are supplied to the uppermost latch circuit 14a through a selector circuit 13a. Thus a circulation loop for circulating the parallel data A to D latched by the latch circuits 14a to 14d is formed. A master clock signal MCK is supplied to a reset circuit 16 and a clock signal CK extracted from the circuit 16 is supplied to the latch circuits 14a to 14d through a selector circuit 15. Consequently the parallel data A to D are circulated and latched by the latch circuits 14a to 14d and the data of the latch circuit 14d e.g. are transmitted to a multiplier 3.
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公开(公告)号：JPH09233491A
公开(公告)日：1997-09-05
申请号：JP3251696
申请日：1996-02-20
Applicant: SONY CORP
Inventor： GAMO NAOYASU
Abstract: PROBLEM TO BE SOLVED: To control any specified chrominance signal and to enable chrominance signal control with a little information. SOLUTION: Based on the control of a microcomputer by the setting operation of an operating part, for example, a chroma serial I/O interface (SIO) 41 generates a prescribed control signal and in the case of converting a color difference signal at a phase/gain control circuit 36, whether a phase or a gain is operated, whether an R-Y signal or a B-Y signal is to be controlled and which quadrant is to be controlled are discriminated. Then, optimum X and Z signals satisfying these discriminated conditions are supplied to a phase/gain control circuit 36B for each picture element. Based on the X and Z signals, the phase/gain control circuit 36B generates the R-Y and B-Y signals from R-G and B-G signals.
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公开(公告)号：JP2000156794A
公开(公告)日：2000-06-06
申请号：JP25971499
申请日：1999-09-14
Applicant: SONY CORP
Inventor： GAMO NAOYASU , SATO MASAAKI
IPC: H04N5/073
Abstract: PROBLEM TO BE SOLVED: To provide an external synchronization system that can realize phase adjustment of a composite synchronizing signal SYNC, only with the addition of a simple circuit when the composite synchronizing signal SYNC is used as a synchronizing signal which is given from a master set and to provide a camera system using the external synchronization system. SOLUTION: In this camera system where a composite synchronizing signal SYNC is used as an externally given synchronizing signal, a horizontal synchronizing signal HD separated by a synchronization separator circuit 14 built into a timing controller IC 13 is once outputted to the outside of the timing controller IC 13, and the phase of the horizontal synchronizing signal HD is adjusted by an external HD phase adjustment circuit 15, and the adjusted horizontal synchronizing signal is again given to the timing controller IC 13 and an internal horizontal synchronizing signal HD' and an internal vertical synchronizing signal VD' that are reference signals of this system are generated, based on the horizontal synchronizing signal HD whose phase is adjusted and on the vertical synchronizing signal VD separated by the synchronization separator circuit 14.
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公开(公告)号：JPH09247499A
公开(公告)日：1997-09-19
申请号：JP5438896
申请日：1996-03-12
Applicant: SONY CORP
Inventor： GAMO NAOYASU
Abstract: PROBLEM TO BE SOLVED: To obtain a gamma correcting circuit where plural gamma curved lines are obtained from min. ROM by storing one gamma curved line and executing the weighing of the gamma curved line. SOLUTION: The gamma correcting circuit 1 is provided with ROM 2 where a luminance signal and a chrominance signal being a video signal are inputted from an input terminal 1a, a gamma OFF straight line generating circuit 3, a two-single straight line generating circuit 4 and a standard level wave detecting circuit 5 in parallel, a multiplier 6 and an adder 7 are connected after ROM 2 and, moreover, an output terminal 9 is connected by way of a switch 8. ROM 2 stores gamma curved line data consisting of data being the double of difference between the normal gamma curved line till the standard level of an input signal and a gamma OFF straight line. The multiplier 6 prepares 16-stages of coefficients. Then, by receiving an instruction from a selecting instruction circuit 6a, a coefficient selecting circuit 6b is triggered and the selected coefficient is multiplied by gamma curved line data. In result, one of the 15 gamma curved line is outputted.
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公开(公告)号：JPH05183465A
公开(公告)日：1993-07-23
申请号：JP36044291
申请日：1991-12-28
Applicant: SONY CORP
Inventor： ISHIKAWA FUMIO , KITAZONO SHINICHI , GAMO NAOYASU
Abstract: PURPOSE:To improve the distortion characteristic of the receiver by connecting a power supply circuit of a mixer circuit and a power supply circuit of an intermediate frequency amplifier circuit in series and connecting both ends of the connection to the power supply so as to increase a DC bias current of the circuits rationally. CONSTITUTION:A voltage Vcc of a power supply 20 is divided into a parallel circuit comprising a parallel circuit section 22 and a voltage regulator 33 and an intermediate frequency amplifier circuit 19 connecting in series with the parallel circuit. Thus, a power supply voltage of almost Vcc/2 is fed respectively to both terminals of the parallel circuit of a local oscillation circuit 14 or 17, a mixer circuit 12 or 15 and the voltage regulator 33 and both terminals of the amplifier circuit 19 each comprising a differential amplifier circuit. Thus, the power supply voltage given to each circuit is halved to increase to double a bias current deciding the operating region of differential pair transistors(TRs) in the mixer circuits 12, 15 and the amplifier circuit 19 by halving the power supply voltage given to each circuit.
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Patent Agency Ranking6.发明专利
公开(公告)号：JP2005303367A
公开(公告)日：2005-10-27
申请号：JP2004112382
申请日：2004-04-06
Inventor： GAMO NAOYASU
Abstract: PROBLEM TO BE SOLVED: To enable processing of a video signal with low power consumption with an inexpensive configuration, and display a video image of a picked-up object with excellent image quality.
SOLUTION: An image pickup section 10 generates the video signal of a picked-up image. A video signal processing device 20 applies video size changing processing or video signal converting processing according to a display unit 30 to the video signal of a picked-up image. The video signal subjected to the processing by a size change processing circuit 231 is held in a register 232. A signal conversion processing circuit 233 performs signal processing using the video signal held in the register 232. A video signal of the picked-up image for which a plurality of signal processes are completed is written into an eDRAM 22, and this written video signal is supplied to the display unit 30 to display a moving image. Thus, the number of times of writing or reading of the video signal into the eDRAM 22 is small, and power consumption is reduced. Also, deterioration in a frame rate can be prevented without widening the band of a transmission path, and the moving image with satisfactory image quality can be performed.
COPYRIGHT: (C)2006,JPO&NCIPIAbstract translation: 要解决的问题：为了能够以廉价的配置对低功耗的视频信号进行处理，并以优异的图像质量显示拍摄对象的视频图像。 解决方案：图像拾取部分10产生拾取图像的视频信号。 视频信号处理装置20将根据显示单元30的视频尺寸改变处理或视频信号转换处理应用于拾取图像的视频信号。 由大小改变处理电路231进行处理的视频信号被保持在寄存器232中。信号转换处理电路233使用保存在寄存器232中的视频信号进行信号处理。 将多个信号处理完成的信号写入eDRAM22，并将该写入的视频信号提供给显示单元30以显示运动图像。 因此，写入或读取到eDRAM 22中的视频信号的次数很少，并且功耗降低。 此外，可以防止在不扩大传输路径的频带的情况下的帧速率的劣化，并且可以执行具有令人满意的图像质量的运动图像。 版权所有（C）2006，JPO＆NCIPI
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7.发明专利
公开(公告)号：JPH1188897A
公开(公告)日：1999-03-30
申请号：JP24100297
申请日：1997-09-05
Applicant: SONY CORP
Inventor： GAMO NAOYASU
IPC: H04N9/07
Abstract: PROBLEM TO BE SOLVED: To provide a false color compressing circuit and method capable of surely reducing the level of a false color at the time of high contrast generated on principle without increasing the number of gates of a main low pass filter(LPF). SOLUTION: Change-over switches 38, 39 are switched by a correction pulse supplied from an OR gate 41 through a detection signal width adjusting circuit 42 and a detection signal phase adjusting circuit 43 at the time of high contrast. Consequently data S2 are substituted for data S1 obtained prior to filtering processing by a pre-LPF 26 and the data S1, S2 are supplied to the main LPF 40 so as to remove a level difference between two inputs of the main LPF 40.
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公开(公告)号：JPH0697733A
公开(公告)日：1994-04-08
申请号：JP27236392
申请日：1992-09-14
Applicant: SONY CORP
Inventor： GAMO NAOYASU , KITAZONO SHINICHI , ISHIKAWA FUMIO
Abstract: PURPOSE:To enlarge a variable range of an oscillation frequency by decreasing the parasitic capacity of a positive feedback path, and enlarging a variation ratio of the variable capacity of an oscillation circuit being parallel to the parasitic capacity like an equivalent circuit. CONSTITUTION:An oscillation output of an oscillation differential amplifier 2 is subjected to positive feedback to a base of a transistor Q2 for forming a differential pair and oscillated through a transistor Q12 of an emitter follower input means 17B. In this case, the parasitic capacity viewed from a resonance circuit 4 becomes equivalent to that which connects the parasitic capacity of Q12 in series to the parasitic capacity of Q3 and Q2 of an amplification stage 3, and becomes that of a small number pF. Accordingly, by forming the parasitic capacity being in parallel to a variable capacitor C3 of the oscillation circuit 4 to an extremely small one and enlarging a variable capacity ratio of C3, a variable range of an oscillation frequency can be enlarged.
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公开(公告)号：JP2005149461A
公开(公告)日：2005-06-09
申请号：JP2004021489
申请日：2004-01-29
Inventor： GAMO NAOYASU , TOSHIDA MASAHIRO
Abstract: PROBLEM TO BE SOLVED: To prevent a reduction or the like in the processing speed of a program and data, in a device using an asynchronous memory and an information processor including the device, by selectively using a control register according to a clock frequency used. SOLUTION: In the information processor 1, a clock source 6 generates a clock to send it to a memory interface part 4 via clock frequency regulating means 7. Memory control means 5 for accessing the asynchronous memory 3 via a memory bus 2 by selectively using clock signals of different frequencies comprise a plurality of control registers 9 corresponding to the clock signal frequencies, and when the clock signal used is changed, select the control register 9 that has a register setting value corresponding to the clock signal. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题为了防止程序和数据的处理速度的降低等，在使用异步存储器的装置和包括该装置的信息处理装置中，通过根据时钟有选择地使用控制寄存器 频率使用。 解决方案：在信息处理器1中，时钟源6产生时钟，经由时钟频率调节装置7将其发送到存储器接口部分4.存储器控制装置5用于经由存储器总线2通过存储器总线2访问异步存储器3 选择性地使用不同频率的时钟信号包括对应于时钟信号频率的多个控制寄存器9，并且当所使用的时钟信号改变时，选择具有对应于时钟信号的寄存器设置值的控制寄存器9。 版权所有（C）2005，JPO＆NCIPI
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10.发明专利
公开(公告)号：JP2003140623A
公开(公告)日：2003-05-16
申请号：JP2001340204
申请日：2001-11-06
Applicant: SONY CORP
Inventor： TANABE HIDEKI , MORITA KOJI , TAMAYAMA KEN , GAMO NAOYASU
Abstract: PROBLEM TO BE SOLVED: To correctly display data which is designed to specific resolution on a PDA according to its screen size. SOLUTION: Low-resolution data which need to be compatible are normally sent out to an image conversion part through data buses LD0 and LD1 (Fig. 10A). The image conversion part two times-magnifies the data from the data bus LD0 laterally and outputs it to an LCD through LCD buses D0 and D1, and two times-magnifies the data from the data bus LD1 laterally and outputs it to the LCD through LDC buses D2 and D3 (Fig. 10B). The LCD latches the data sent through the LCD bus D0 to D3 successively according to clock pulses (CLK) and outputs latched data of one line longitudinally twice according to double pulses (DBLLP). Consequently, the data which need to be compatible are two times-magnified laterally and longitudinally and displayed on the LCD.
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