公开(公告)号：JPH07211806A

公开(公告)日：1995-08-11

申请号：JP269994

申请日：1994-01-14

Applicant: SONY CORP

Inventor： MAARI KOUICHI

IPC: H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To realize a semiconductor nonvolatile storage device and its manufacturing method wherein the manufacturing process can be reduced, and furthermore the cost can be reduced. CONSTITUTION:In a semiconductor nonvolatile storage device which has a floating gate 16, and a control gate 18 formed on the floating gate 16, the floating gate 16, in which the side wall is involved, is covered with the control gate 18, and a source diffusion layer 12 and a drain diffusion layer 13 are constituted so as to overlap the floating gate 16. Thereby, in the manufacturing process, the patterning of the floating gate after the patterning of the control gate is made unnecessary, and the manufacturing process can be reduced.

公开(公告)号：JPH07130891A

公开(公告)日：1995-05-19

申请号：JP29745393

申请日：1993-11-02

Applicant: SONY CORP

Inventor： MAARI KOUICHI

IPC: H01L21/8247 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To increase unction breakdown strength in the diffusion layers of transistors being formed in a well and having different threshold voltage, and to estimate alignment allowance at a large value. CONSTITUTION:The ions of impurities for forming a P well 41 and impurities 24 for determining the threshold voltage of an enhancement type transistor 14 are implanted onto a region, in which the P well 41 must be formed, while using a photo-resist having an opening as a mask. The ions of impurities 27 for determining the threshold voltage of a depletion type transistor 15 are implanted while employing the photo-resist 43 as the mask. Accordingly, the P well 41 is formed only of the single photo-resist, thus equalizing the impurity concentration of the P well 41.

公开(公告)号：JPH07130725A

公开(公告)日：1995-05-19

申请号：JP29399893

申请日：1993-10-29

Applicant: SONY CORP

Inventor： MAARI KOUICHI

IPC: H01L21/316 ,  H01L21/76 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To improve the reliability of a semiconductor device comprising an element having a thin gate oxide film and an element for driving at a high voltage, both formed on a semiconductor substrate. CONSTITUTION:A semiconductor device has a first element isolating thick film 11, a first element 13 isolated by this film, a second element isolating thin film 12 and a second element 14 isolated by this film on a semiconductor substrate 102. The element 13 is comprises a thick insulation film 102 formed on the upper side of the substrate 101 and a conductive layer 103 formed on the upper side of the film 102. The element 14 has a floating gate 106 and a thin insulation film 104 is formed on the substrate 101. A high driving voltage is applied to the element 103, thereby suppressing the edge part of the film 104 of the second element from being thinned.

公开(公告)号：JPH06275847A

公开(公告)日：1994-09-30

申请号：JP6546593

申请日：1993-03-24

Applicant: SONY CORP

Inventor： MAARI KOUICHI

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To provide a semiconductor device and its manufacture, in which a satisfactory contact structure being little in the variation of transistor characteristics can be realized in the semiconductor device with an ordinary transistor existing in an array of transistors having a floating gate. CONSTITUTION:The title semiconductor device has a struture, in which a memory-cell transistor 2 having a floating gate 11 and a selective transistor 4 having no floating gate are connected in series via diffused impurity layer 40 formed on the surface of a semiconductor substrate, and an upper layer side wiring layer 48 is connected with the diffused impurity layer 40 via contact hole 54. An etching groove 52 formed on the surface of the semiconductor substrate placed between the memory-cell transistor 2 and selective transistor 4 is formed in a position near to the selective transistor 4 side and the contact hole 54 is formed so as not to overlap with the etching groove 52.

公开(公告)号：JPH05304302A

公开(公告)日：1993-11-16

申请号：JP13157692

申请日：1992-04-24

Applicant: SONY CORP

Inventor： MAARI KOUICHI

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To pattern a conductive film with a space width finer than the limit of lithographic technology. CONSTITUTION:An SiN film 26 is patterned on a poly-Si film 14 such that the edge of a space to be provided between floating gates in the extending direction of control gate is aligned, on one side thereof, with the edge of the SiN film 26. A thin SiO2 film 27 having good step coverage is then deposited thereon followed by flat coating of photoresist 31. The photoresist 31 is then etched back to expose the SiO2 film 27, which is subsequently subjected to isotropic etching, and the poly-Si film 14 is etched anisotropically with the SiN film 26 and the photoresist 31 as a mask. This method provides a space width between poly-Si films 14 equal to the thickness of the SiO2 film 27.

公开(公告)号：JPH10271011A

公开(公告)日：1998-10-09

申请号：JP7418497

申请日：1997-03-26

Applicant: SONY CORP

Inventor： MAARI KOUICHI

IPC: H03M7/30 ,  G09C1/00

Abstract: PROBLEM TO BE SOLVED: To improve the security of digital data distributed through a network. SOLUTION: A device has a common key encryption decoding circuit 24 that decodes encrypted and compressed digital data for each processing bit number of the decoding algorithm, a buffer memory 25 that stores tentatively the decoded data in the unit of bits of a least common multiple of a processing bit number of the decoding algorithm and a processing bit number of the expansion algorithm, and an expansion circuit 26 that reads and expands the data stored in the buffer memory 25 for each processing bit of the expansion algorithm.

公开(公告)号：JPH10269289A

公开(公告)日：1998-10-09

申请号：JP7418297

申请日：1997-03-26

Applicant: SONY CORP

Inventor： MAARI KOUICHI

IPC: G06F1/00 ,  G06F9/06 ,  G06F12/14 ,  G06F15/00 ,  G06F21/00 ,  G06F21/10 ,  G06F21/12 ,  G06F21/14 ,  G06F21/60 ,  G06F21/62 ,  G06Q10/00 ,  G06Q20/00 ,  G06Q20/28 ,  G06Q20/32 ,  G06Q30/04 ,  G06Q30/06 ,  G06Q50/00 ,  G06Q50/10 ,  G09C1/00 ,  G10K15/02 ,  G11B20/00 ,  H04L9/08 ,  H04L12/14 ,  H04L29/06 ,  H04M15/00 ,  G06F17/60

Abstract: PROBLEM TO BE SOLVED: To construct an easily portable and also economical system that makes a player enjoy digital contents at any time in any place and that sufficiently resists application as defence against illegal usage, by decoding the processed digital contents with a content key and also extending and reproducing them. SOLUTION: A player 1 is provided with at least a common key cipher decoding circuit 24 decoding the ciphered digital contents through the use of the content key, an extending circuit 26 being an extending means for extending the compressed digital contents and a D/A converting circuit 27 converting digital data into an analog signal. When the player 1 is the one who is registered in the system, he can freely copy the ciphered contents so as to appreciate the contents only by obtaining the content key. Therefore, the ciphered contents are easily installed in storage media.

公开(公告)号：JPH08222649A

公开(公告)日：1996-08-30

申请号：JP2976795

申请日：1995-02-17

Applicant: SONY CORP

Inventor： MAARI KOUICHI ,  ARASE KENSHIROU

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To realize a semiconductor nonvolatile memory having enhanced memory characteristics. CONSTITUTION: Threshold voltage of select transistors ST1, ST2 is set closely to 0.3V which is lower than the threshold voltage (0.7-0.8V) of a normal transistor. Consequently, the operating speed can be enhanced at the time of reading thus enhancing the memory characteristics. At the time of writing, a select transistor to be connected with a sub-bit line on the unselect side is applied, to the gate thereof, with a positive voltage higher by 0-0.3V than the threshold voltage Vth thereof. Consequently, the sub-bit line on the unselect side can be protected from floating. In this regard, the threshold voltage of select transistor may have a regular value (0.7-0.8V).

公开(公告)号：JPH0864695A

公开(公告)日：1996-03-08

申请号：JP22247594

申请日：1994-08-24

Applicant: SONY CORP

Inventor： MAARI KOUICHI

IPC: H01L27/112 ,  H01L21/8246

Abstract: PURPOSE: To make TAT to be short and form a contact hole stably by making a contact hole in respective memory cell and connecting a wiring layer to a contact hole of specified memory cell thereafter. CONSTITUTION: After a plurality of memory cells consisting of gate area 14 and source and drain areas 15A and 15B are formed on a semiconductor substrate 10, a first interlayer insulation layer 20 is entirely formed thereon and an opening part 21 is formed in an interlayer insulation layer 20 above the source and drain area 15A of the respective memory cell. Next, after a metallic wiring material 22 is embedded into the opening part 21 to form a contact hole, a second interlayer insulation layer 23 is formed on the material 22 and the layer 20. Further, a second opening part 24 is formed in a second interlayer insulation layer 23 on the contact hole of the specified memory cell and a wiring layer 25 electrically connecting with the contact hole through a second opening part 24 is formed on the second interlayer insulation layer 23.

公开(公告)号：JPH07130893A

公开(公告)日：1995-05-19

申请号：JP30113993

申请日：1993-11-05

Applicant: SONY CORP

Inventor： MAARI KOUICHI

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To obtain high sustaining characteristics while realizing operation at high speed regarding charges infected into a floating gate, and to improve the degree of freedom of the design of a memory section. CONSTITUTION:A polycrystalline Si layer 31 is used as a floating gate, a diffusion layer 21 as a control gate and a high melting-point metallic layer 33 as a wiring, etc., in the memory cell 11 in the memory cell 11. A polycide layer 36 consisting of a polycrystalline Si layer 32 and a high melting-point metallic layer 34 is employed as the gate electrode of a transistor 12 in a peripheral circuit section. Accordingly, an excellent insulating film 26 can be formed around the floating gate by the thermal oxidation, etc., of the surface of the polycrystalline Si layer 31.