公开(公告)号：JP2002077839A

公开(公告)日：2002-03-15

申请号：JP2000253334

申请日：2000-08-24

Applicant: SONY CORP

Inventor： MAARI KOUICHI

IPC: G06Q30/06 ,  G06Q50/00 ,  H04N5/44 ,  H04N5/445 ,  H04N5/765 ,  H04N7/14 ,  H04N7/173 ,  H04N19/00 ,  H04N19/40 ,  H04N21/222 ,  H04N21/2747 ,  G06F17/60 ,  H04N7/24

Abstract: PROBLEM TO BE SOLVED: To make possible to view a digital broadcast even on a potable information terminal. SOLUTION: In a digital portable telephone 50 with camera, an image recording server 11 is designated to record a program of digital broadcast. The image recording server 11 receives a designated program through a receiver 11, decodes it through a decoder 112 and encodes it through an encoder 113 suitably for the digital portable telephone 50 with camera. Encoded content data is stored in a storage unit 114. When a user views a recorded program, the user request the image recording server 11. In response to the request, the image recording server 11 reads out a requested content data from the storage unit 114 and delivers it to the digital portable telephone 50 with camera.

公开(公告)号：JPH08204158A

公开(公告)日：1996-08-09

申请号：JP698395

申请日：1995-01-20

Applicant: SONY CORP

Inventor： MAARI KOUICHI

IPC: H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To increase the memory speed and the level of integration of a semiconductor storage device wherein bit lines are divided into a main bit line and subbit lines. CONSTITUTION: In a semiconductor storage device having a plurality of subbit lines SBL which are respectively connected with a plurality of memory transistors MT, and a main bit line MIL with which the subbit lines SBL are selectively connected, an auxiliary wiring layer EL which is electrically isolated from the main bit line is formed by using the same conducting layer as a conducting layer which constitutes the main bit line MIL, and the auxiliary wiring layer EL is connected with the subbit lines SBL.

公开(公告)号：JPH0823040A

公开(公告)日：1996-01-23

申请号：JP15688494

申请日：1994-07-08

Applicant: SONY CORP

Inventor： MAARI KOUICHI

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To provide a flush EEPROM having a high degree of integration and a high writing-in and erasing efficiency. CONSTITUTION:Silicon supporting poles 12 are uprightly provided on a silicon substrate 11, the circumference of the supporting pole are covered by the first oxide film 13 and the second oxide film 14, and a floating gate 15, the third oxide film 16 and a control gate 17 are formed around the above-mentioned oxide films 13 and 14. The rows of the supporting poles 12 are connected by a bit line 20. By having the above-mentioned constitution, the degree of integration can be improved and the coefficient of coupling can also be secured. As a result, the efficiency in a writing-in and erasing operations can be improved.

公开(公告)号：JPH07115177A

公开(公告)日：1995-05-02

申请号：JP25871193

申请日：1993-10-15

Applicant: SONY CORP

Inventor： ARASE KENSHIROU ,  MAARI KOUICHI

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/02

Abstract: PURPOSE:To avoid a reading gate disturb caused at the time of data reading by a method wherein a threshold voltage when charge is not stored in a charge storing part is set at a value between a threshold voltage at the time of writing and a threshold voltage at the time of erasing. CONSTITUTION:N-type impurities, for instance P ions or As ions, are implanted into the P-type channel forming part of a memory cell transistor to form a low impurity concentration N-type layer, i.e., a buried channel layer 4. A threshold voltage when there is no charge in a floating gate FG is set at 0--1 V which is lower than the conventional set value of 1-2 V. That is, a threshold voltage when there is no charge in a floating gate FG is set at a value between a threshold voltage when charge does not exist in the floating gate FG and a threshold voltage when plus charge exists in the floating gate FG.

公开(公告)号：JPH06310456A

公开(公告)日：1994-11-04

申请号：JP12359593

申请日：1993-04-27

Applicant: SONY CORP

Inventor： MAARI KOUICHI

IPC: H01L21/265 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To eliminate deterioration of a transistor threshold voltage, channel leakage current, etc., by ion-implanting impurities on a polycrystal semiconductor film formed on a semiconductor substrate at an implanting angle in a specific range. CONSTITUTION:After forming an SiO2 film 12 on the surface of an Si substrate 11, a polycrystalline Si film 13 us accumulated on the whole plane by CVD. Then, an impurity 18 such as phosphorus is ion-implanted on the polycrystalline Si film 13 at an implanting angle of 45 deg.. The grain boundary of the polycrystalline Si film 13 often expands at an angle close to vertical to the surface of the Si substrate 11. However, since the angle between the direction of the grain boundary of the polycrystalline Si film 13 and the direction of the ion implantation is large at 45 deg., the ion-implanted impurity 18 does not reach the Si substrate 11 along the grain boundary. Therefore, an excellent characteristic flash EEPROM which does not allow transistor threshold voltage deterioration, channel leak current, etc., is manufactured.

公开(公告)号：JPH06291288A

公开(公告)日：1994-10-18

申请号：JP7993093

申请日：1993-04-07

Applicant: SONY CORP

Inventor： NAKAJIMA HIDEHARU ,  YAMAZAKI TAKESHI ,  MAARI KOUICHI

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To enable reduction of a source part and to enable rapid operation by resistance reduction of a source line by connecting a common source part of a memory cell transistor with a low resistance wiring. CONSTITUTION:When ion implantation is performed for a source/drain region, ion implantation is also performed for a common source line. Then, a contact hole 4 is shaped in each source. Thereafter, a first polysilicon film 5 is deposited. Impurity diffusion is performed for the first polysilicon film 5. A source line 5A is patterned. The source line 5A reduces a source resistance by connecting each source 1A. Thereby, rapid operation is possible. Furthermore, it is possible to prevent rising of a source potential of a memory cell far from a part wherein contact is taken from a common source contact to an A1 wiring, for example.

公开(公告)号：JP2009213012A

公开(公告)日：2009-09-17

申请号：JP2008055949

申请日：2008-03-06

Applicant: Sony Corp ,  ソニー株式会社

Inventor： IWASA HIROSHI ,  MAARI KOUICHI ,  UENO TAKAHISA

IPC: H04N5/335 ,  H04N5/369 ,  H04N5/374 ,  H04N5/376

Abstract: PROBLEM TO BE SOLVED: To enhance an yield caused by a defect by relieving the relevant defect in an analog circuit of a column processing section.
SOLUTION: In a column processing section 13A, current sources 32-1 to 32-4 and comparators 33-1 to 33-4, which are portions of an analog circuit, are provided more than the number of pixel columns one by one and in a case where there is a defect in a certain current source or comparator, it is substituted with another normal current source or comparator, namely, the portions in the analog circuit of the column processing section 13A are configured redundantly. On the basis of shift register information in a predetermined shift register 36, a defective portion is substituted with a normal circuit.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：通过减轻列处理部分的模拟电路中的相关缺陷来提高由缺陷引起的产量。 解决方案：在列处理部分13A中，作为模拟电路的一部分的电流源32-1至32-4和比较器33-1至33-4被提供多于像素列的数目1 一个在某一电流源或比较器存在缺陷的情况下，由另一个正常电流源或比较器代替，即列处理部分13A的模拟电路中的部分被冗余地配置。 基于预定移位寄存器36中的移位寄存器信息，用普通电路代替缺陷部分。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2003174468A

公开(公告)日：2003-06-20

申请号：JP2001372947

申请日：2001-12-06

Applicant: SONY CORP

Inventor： MAARI KOUICHI

IPC: G06K19/00 ,  G06F13/00 ,  G06K7/10 ,  G06K17/00 ,  G06K19/07 ,  H04L12/70 ,  H04N5/44 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To easily and speedily form a private network. SOLUTION: When an IC card 1 is made proximate to the IC card reader/ writer of a hard disk recorder 3, the hard disk recorder 3 writes a profile containing its own IP address or the like on the IC card 1. When a profile list containing a card ID and the profile of a television receiver 2, for example, is read out of the IC card 1, the hard disk recorder 3 performs access to the television receiver 2 on the basis of the list. Then, the hard disk recorder 3 reports the profile list read out of the IC card 1 and newly added with the profile of the hard disk recorder 3 to the television receiver 2 and forms a Virtual Private Network (VPN) 5 with the television receiver 2. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003173308A

公开(公告)日：2003-06-20

申请号：JP2001372946

申请日：2001-12-06

Applicant: SONY CORP

Inventor： MAARI KOUICHI

IPC: G06F12/14 ,  G06F13/00 ,  G06F21/00 ,  G06F21/10 ,  G06F21/34 ,  G06F21/62 ,  G06K17/00 ,  G06Q10/00 ,  G06Q30/04 ,  G06Q30/06 ,  G06Q50/00 ,  G06Q50/10 ,  G07F7/08 ,  G07F7/12 ,  H04N7/16 ,  G06F15/00 ,  G06F17/60

Abstract: PROBLEM TO BE SOLVED: To allow the more free use of contents while suppressing unlimited copying. SOLUTION: When an IC card 1 gets close to a television receiver 2, a hard disc recorder 3 and a PDA 4, the card ID stored in the IC card 1 and the profile of the equipment are shared to form a VPN (virtual private network) 5. When the download of a content is requested from the hard disc recorder 3, a content delivery server 161 transmits the content according to the request to store it in the hard disc recorder 3. When the regeneration of the stored content on the television receiver 2 is instructed, the authentication between the hard disc recorder 3 and the television receiver 2 is performed on the basis of the card ID, and the content is transmitted to the television receiver 2 when the television receiver 2 is authenticated. COPYRIGHT: (C)2003,JPO

公开(公告)号：JPH0823081A

公开(公告)日：1996-01-23

申请号：JP15688594

申请日：1994-07-08

Applicant: SONY CORP

Inventor： MAARI KOUICHI

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To provide a semiconductor device which is lessened in writing/erasing voltage and expanded in error writing margin and where a contact-less array directly connected to a memory cell is realized. CONSTITUTION:A polysilicon film 22 serving as a floating gate and a polysilicon film 24 serving as a control gate are formed on a silicon substrate 11 by patterning, the source 17 of a MOS transistor is set lower enough than the drain 16 in impurity concentration. By this setup, a semiconductor device of this constitution can be protected against error writing and lessened in voltage required for writing/erasing.