公开(公告)号：JPH0225261B2

公开(公告)日：1990-06-01

申请号：JP3696486

申请日：1986-02-21

Applicant: SONY CORP

Inventor： OOTSU KOJI ,  MOCHIZUKI HIDENOBU ,  SHIMADA TAKASHI

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78

公开(公告)号：JPH02143527A

公开(公告)日：1990-06-01

申请号：JP29617588

申请日：1988-11-25

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L21/3205

Abstract: PURPOSE:To enable the buried wiring process in fine patterns or deep grooves to be executed by selective deposition by a method wherein a conductor layer to be the seed of selective deposition is formed to be selectively deposited after patterning the conductor layer to form insulating films between the patterns. CONSTITUTION:A polysilicon layer 2 as a conductor layer to be the seed of selective deposition is formed on a silicon oxide 1 as a substrate, a resist layer formed on the layer 2 is patterned for patterning the layer 2 using the resist layer as a mask. First, the second silicon oxides 3 are formed between the layers 2. Secondly, the layers 2 is selectively etched away in thin thickness of t1. At this time, sidewalls 3s are exposed to the space between the patterns held by the sidewalls 3s leaving the thin polysilicon layers 2 on the bottom parts. Finally, Cu layers 4 are selectively deposited on the upper parts of the silicon layers 2 held by the sidewalls 3s using the residual silicon layers 2 as the seeds of crystalline deposition. Through these procedures, the flat buried wiring process is enabled to be executed.

公开(公告)号：JPH01297824A

公开(公告)日：1989-11-30

申请号：JP12798488

申请日：1988-05-25

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3205

Abstract: PURPOSE:To reduce contamination of a semiconductor substrate by selectively removing a surface of a substrate by photo-etching in a reaction device, and successively forming a layer on a portion selectively removed by photo-CVD in the same reaction device. CONSTITUTION:A semiconductor substrate 2 is put in a reaction device 1, and the interior of the device is heated to a temperature suitable for photo-etching by a heater 3. Then, Si etching gas is supplied into the reaction device 1, and a semiconductor substrate 2 surface is selectively irradiated with a laser beam 5 which said gas is exhausted for an exhaust port 4. A region on the semiconductor substrate 2 surface which is selectively irradiated with the laser beam 5 is etched to form a trench. Thereafter, SiO2 CVD gas is supplied into the reaction device 1, and the region which has been irradiated with the laser beam 5 upon the photo-etching is again irradiated with the laser beam 5. Hereby, an insulating layer is formed on the region irradiated with the laser beam 5, and the trench having been formed is burried with the insulating layer. Thus, a semiconductor device without any contamination on the semiconductor substrate can be produced.

公开(公告)号：JPS6267873A

公开(公告)日：1987-03-27

申请号：JP20795885

申请日：1985-09-20

Applicant: SONY CORP

Inventor： KOBAYASHI KAZUYOSHI ,  SHIMADA TAKASHI

IPC: H01L29/78 ,  H01L21/265

Abstract: PURPOSE:To contrive the miniaturization of a semiconductor element by forming a gate electrode whose surface is covered with an insulating film and forming an electrode to be connected to a semiconductor region on the surface part of a semiconductor substrate after forming an insulating film on the side walls of said gate electrode. CONSTITUTION:After forming a low resistance polysilicon layer 7 on a substrate 1 by doping N-type impurities, a nitride layer 8 is formed on the surface of the polysilicon layer 7. The nitride layer 8 and the polysilicon layer 7 are etched by photo-etching to form a silicon gate electrode 9 having a nitride non- oxidizable film 10 on its surface. After that, unnecessary parts located above a source forming region and a drain forming region of a gate insulating film 6 are removed. The side parts of the silicon gate electrode 9 are heat-oxidized at about 750 deg.C which is a relatively low temperature as an oxidation temperature for silicon by using the non-oxidizable film 10 as a mask. Next, after forming an aluminum film, it is photo-etched to form electrodes 17, 17 to be connected with a source 15 and a drain 16.

公开(公告)号：JPS6237967A

公开(公告)日：1987-02-18

申请号：JP17731785

申请日：1985-08-12

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/417

Abstract: PURPOSE:To prevent the etch-off of a gate oxide film, by attaching a first conducting layer on the gate oxide film, performing the photoetching of a contact region, and performing light etching of a low grade oxide film, which is grown in the contact region. CONSTITUTION:At first, an LOCOS oxide film 3 is formed on an Si substrate 1 then a gate oxide film 2 is formed. Thereafter, polycrystalline Si 4a is attached on the entire surface. Then, with photoresist 5 as a mask, etching is performed, and a part of the Si layer 4A, which is to become a contact region in the future, is removed. Thereafter, the photoresist 5 is removed. A low grade oxide film 11, which has been grown in etching, is removed by light etching. Then, a polycrystalline Si layer 4b is attached. A gate electrode, a wiring electrode part and an etching groove 6 are formed by etching. A contact region 10, a source region 8 and a drain region 9 are formed. Thus, an embedded contact is completed.

公开(公告)号：JPS6042633B2

公开(公告)日：1985-09-24

申请号：JP6853978

申请日：1978-06-07

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI ,  OOTSU KOJI

IPC: H01L27/112 ,  G11C11/40 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

公开(公告)号：JPS6042632B2

公开(公告)日：1985-09-24

申请号：JP1272878

申请日：1978-02-07

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI ,  OOTSU KOJI ,  MOCHIZUKI HIDENOBU

IPC: H01L21/8234 ,  H01L21/8247 ,  H01L27/088 ,  H01L29/788 ,  H01L29/792

公开(公告)号：JPS5873150A

公开(公告)日：1983-05-02

申请号：JP17179881

申请日：1981-10-27

Applicant: SONY CORP

Inventor： OKAZAKI NOBUMICHI ,  SHIMADA TAKASHI

IPC: H01L29/78 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/11

Abstract: PURPOSE:To reduce the thickness of the resistor layer of the titled semiconductor device by a method wherein a resistor layer is formed in the under-layer in such a manner that almost no step is generated thereon. CONSTITUTION:A source region 12 and a drain region 13 are formed on one main surface of an Si semiconductor substrate 11, and a thick insulating layer 15 is formed around these regions 12 and 13. Also, a gate insulating layer 14 is formed between the regions 12 and 13, and electrode windows 15a and 15d are formed on the regions 12 and 13. Then, a patternized high resistance layer 18, to be connected to the region 13, is formed on the layer 15. The layer 18 is to be formed in sufficiently thin thickness. An insulating layer 17 is formed in such a manner that it covers the layer 18. A window is opened at one end part of the insulating layer 17, which will be connected to the region 13, and at the other end part on the reverse side, and the layer 17 on the window 15a and the layer 14 is removed. Subsequently, a source electrode 16s, a drain electrode 16d, a gate electrode 18g, and a wiring pattern 16p, to be connected to the other end part of the layer 18, are formed. According to this constitution, the semiconductor device can be microscopically formed because the layer 18 formed in sufficiently thin thickness.

公开(公告)号：JPS5775455A

公开(公告)日：1982-05-12

申请号：JP15195580

申请日：1980-10-29

Applicant: Sony Corp

Inventor： HIRATA YOSHIMI ,  KAMATA MIKIO ,  SHIMADA TAKASHI

IPC: H01L21/339 ,  H01L27/148 ,  H01L29/762 ,  H04N5/335 ,  H04N5/341 ,  H04N5/347 ,  H04N5/355 ,  H04N5/359 ,  H04N5/369 ,  H04N5/3725

CPC classification number: H01L27/14887

Abstract: PURPOSE:To obtain a picture element with high density by forming junction type overflow drain regions on separating regions which are used for separating transfer regions. CONSTITUTION:A plurality of N type transfer regions 22 which are partitioned by P type separating regions 21 are formed in a P type Si substrate 20. A shallow N type separating region 23 is formed in each region 22. A highly concentrated P type overflow drain region 24 is formed corresponding to each region 23. In this constitution, a specific bias voltage is applied to the region 24 during the period of light receiving. When the overflow begins due to the excessive reception of the light during the light receiving period, the electric charges flow from one region 22 to the adjacent region 22. When the adjacent region 22 is overflowed, the excessive charges are absorbed by the region 24 as minority carriers, and a stable state is obtained. During the charge transfer period, the P-N junction is reversedly biased by raising the potential at the region 24 to the zero side, the potential at the region 23 is raised, and the right and left regions 22 are separated. Under this state, the signal charges can be excellently transferred.

Abstract translation: 目的：通过在用于分离转印区域的分离区域上形成结型溢流漏区，以获得高密度的像素。 构成：在P型Si衬底20中形成由P型分离区21划分的多个N型转移区22.在每个区22中形成浅N型分离区23.高浓度P + 类型溢出漏极区域24形成为对应于每个区域23.在该结构中，在光接收期间，特定的偏置电压被施加到区域24。 当在光接收期间由于光的过度接收而溢出开始时，电荷从一个区域22流向相邻区域22.当相邻区域22溢出时，过多的电荷被区域24吸收，如 少数载体和稳定状态。 在电荷转移期间，通过将区域24上的电位升高到零一侧，将P-N结反向偏置，区域23处的电位升高，左右区域22分离。 在这种状态下，信号电荷可以很好的传输。

公开(公告)号：JPS5768066A

公开(公告)日：1982-04-26

申请号：JP14472480

申请日：1980-10-16

Applicant: Sony Corp

Inventor： KAMATA MIKIO ,  HIRATA YOSHIMI ,  SHIMADA TAKASHI

IPC: H01L27/148 ,  H01L31/10

CPC classification number: H01L27/14887

Abstract: PURPOSE:To eliminate a defect in a picture in a solid state image pickup element by enhancing the potential barrier of a channel stopper at the charge transfer time higher than that at the charge storage time, thereby completely transferring the full signal charge stored in the picture elements. CONSTITUTION:N type layer 21 and N type layers 9 are formed at the prescribed interval on a P type Si substrate 6, and a polysilicon layer 13 is formed via a gate insulating film 10. Ions are injected via the mask 13 to form a channel 7 and an N type channel stopper 8. An SiO214 is formed on the layer 13, a transfer electrode 11 is formed, and an objective solid state image pickup element is obtained. With this construction, it has electrodes 13 independently controllable, the balance of the maximum charge storage amount of each channel 7 can be maintained, and when the barrier potential is maintained at lower during the storage period and at higher during the transfer period, defect in the picture can be, even if there is an irregularity in each barrier potential at the storage time, avoided.

Abstract translation: 目的：通过在比电荷存储时间更高的电荷转移时间增强通道阻挡层的势垒来消除固态摄像元件中的图像中的缺陷，从而完全转印存储在图像中的全部信号电荷 元素。 构成：在P型Si衬底6上以规定的间隔形成N +型层21和N +型层9，并且经由栅极绝缘膜10形成多晶硅层13。 掩模13形成通道7和N型通道阻挡器8.在层13上形成SiO 214，形成转移电极11，并获得目标固态图像拾取元件。 利用这种结构，电极13可独立控制，可以维持每个通道7的最大电荷存储量的平衡，并且当屏蔽电位在储存期间维持在较低位置时，并且在转移期间更高， 即使在存储时间内每个障碍势能有不规则的情况，图片也可以避免。