公开(公告)号：DE2536277A1

公开(公告)日：1976-03-04

申请号：DE2536277

申请日：1975-08-14

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI ,  SAIKI SHINICHI ,  KAYANUMA AKIO

IPC: H01L21/00 ,  H01L21/331 ,  H01L27/07 ,  H01L29/00 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/73 ,  H01L29/74 ,  H01L29/72

Abstract: A semiconductor device is disclosed which has a first semiconductor layer of one conductivity type and low impurity concentration, a second semiconductor region of the opposite conductivity type forming a PN junction with the first semiconductor layer, a third semiconductor region of the first mentioned conductivity type formed in the first semiconductor layer which surrounds the PN junction and forms an LH junction with the first semiconductor layer, a passivating layer covering at least the PN and LH junctions, and a conductive layer extending on the passivating layer covering at least the inner periphery of the third region and connected to the first semiconductor layer through an electric barrier layer.

公开(公告)号：CA1037160A

公开(公告)日：1978-08-22

申请号：CA233136

申请日：1975-08-08

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI ,  SAIKI SHINICHI ,  KAYANUMA AKIO

IPC: H01L21/00 ,  H01L21/331 ,  H01L27/07 ,  H01L29/00 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/73 ,  H01L29/74 ,  H01L29/34 ,  H01L29/48

Abstract: OF THE DISCLOSORE A semiconductor device is disclosed which has a first semiconductor layer of one conductivity type and low impurity concentration, a second semiconductor region of the opposite conductivity type forming a PN junction with the first semiconductor layer, a third semiconductor region of the first mentioned conductivity type formed in the first semiconductor layer which surrounds the PN junction and forms an LH junction with the first semiconductor layer, a passivating layer covering at least the PN and LH junctions, and a conductive layer extending on the passivating layer covering at least the inner periphery of the third region and connected to the first semiconductor layer through an electric barrier layer.

公开(公告)号：CA1094221A

公开(公告)日：1981-01-20

申请号：CA272825

申请日：1977-02-28

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI ,  INOUE KENICHI ,  OHTSU TAKAJI ,  MOCHIZUKI HIDENOBU ,  YAMAGUCHI JIRO

IPC: H01L21/8247 ,  H01L21/265 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40 ,  H01L29/76

Abstract: In a memory type insulated gate field effect semiconductor device including a semiconductor layer of one conductivity type, a source region of the opposite conductivity type formed in the surface of the semiconductor layer, a drain region of the opposite conductivity type formed in the surface of the semiconductor layer, a gate insulating layer affixed to the surface of the semiconductor layer, and a gate electrode deposited on the surface of the gate insulating layer, the gate insulating layer has a pair of thick gate guarding portions which exit on side of the source and drain regions, and a thin memory portion intermediate between the thick gate guarding portions, and a surface impurity concentration per square centimeter of the semiconductor layer under the thick gate guarding portions is different from a surface impurity concentration per square centimeter of the semiconductor layer under the tin memory portion. The voltage difference between the threshold voltages of the semiconductor device at the memorized state and at the non-memorized state can be increased, and the readout voltage of the semiconductor device can be reduced. The circuit design is simplified.

公开(公告)号：DE2708599A1

公开(公告)日：1977-09-08

申请号：DE2708599

申请日：1977-02-28

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI ,  INOUE KENICHI ,  YAMAGUCHI JIRO ,  OTSU TAKAJI ,  MOCHIZUKI HIDENOBU

IPC: H01L21/8247 ,  H01L21/265 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: In a memory type insulated gate field effect semiconductor device including a semiconductor layer of one conductivity type, a source region of the opposite conductivity type formed in the surface of the semiconductor layer, a drain region of the opposite conductivity type formed in the surface of the semiconductor layer, a gate insulating layer affixed to the surface of the semiconductor layer, and a gate electrode deposited on the surface of the gate insulating layer, the gate insulating layer has a pair of thick gate guarding portions which exit on side of the source and drain regions, and a thin memory portion intermediate between the thick gate guarding portions, and a surface impurity concentration per square centimeter of the semiconductor layer under the thick gate guarding portions is different from a surface impurity concentration per square centimeter of the semiconductor layer under the tin memory portion. The voltage difference between the threshold voltages of the semiconductor device at the memorized state and at the non-memorized state can be increased, and the readout voltage of the semiconductor device can be reduced. The circuit design is simplified.

公开(公告)号：JP2581097B2

公开(公告)日：1997-02-12

申请号：JP21757887

申请日：1987-08-31

Applicant: SONY CORP

Inventor： KOBAYASHI KAZUYOSHI ,  SUGANO YUKYASU ,  SHIMADA TAKASHI

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L27/12 ,  H01L29/786

公开(公告)号：JPH07147327A

公开(公告)日：1995-06-06

申请号：JP29573893

申请日：1993-11-25

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L21/316 ,  H01L21/761 ,  H01L21/8238 ,  H01L27/092

Abstract: PURPOSE:To achieve the high integration of a semiconductor device, such as a CMOS-LSI or the like, in which an impurity diffused layer of a first conductivity type and an impurity diffused layer of a second conductivity type are arranged so as to be adjacent by being isolated by an element isolation region. CONSTITUTION:A semiconductor device in which a first impurity diffused layer of a first conductivity type and a second impurity diffused layer of a second conductivity type opposite to the first conductivity type are arranged so as to be adjacent on a semiconductor substrate 34 by being isolated by a LOCOS element isolation region is improved. A well which is formed at the lower part of the first impurity diffused layer is formed in a self-aligned manner with the element isolation region. The well is formed by an oblique ion implantation method. In addition, a well 42b may be constituted of a self-aligned well part 51 and of a non-self-aligned well part 52.

公开(公告)号：JPH05109887A

公开(公告)日：1993-04-30

申请号：JP29387291

申请日：1991-10-15

Applicant: SONY CORP

Inventor： TAKAHASHI HIROSHI ,  SHIMADA TAKASHI ,  TOKUNAGA KAZUHIKO

IPC: H01L21/265 ,  H01L21/316 ,  H01L21/336 ,  H01L21/76 ,  H01L29/78

Abstract: PURPOSE:To provide the manufacturing method, of a semiconductor device, which can prevent a crystal defect from being caused in the semiconductor device by a method wherein a stress caused by an element structure from a damage layer, in a silicon substrate, which is produced by an ion implantation operation is removed. CONSTITUTION:The title manufacture is composed of the following: a process which forms an element isolation insulating film 10 on a silicon substrate 1 in such a way that the surface 14 of the element isolation insulating film 10 is situated on the same plane as the surface 3 of the silicon substrate 1 or on the upper part than the surface 3 of the silicon substrate 1; a process in which high-concentration impurities are ion-implanted; a process in which one part of the insulating film 10 is etched in such a way that the surface 14 of the element isolation insulating film 10 is situated at the lower part of the surface 3 of the silicon substrate 1; and a process in which the impurities are activated and annealed.

公开(公告)号：JPH036058A

公开(公告)日：1991-01-11

申请号：JP14056589

申请日：1989-06-01

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L29/41 ,  H01L21/28 ,  H01L29/43

Abstract: PURPOSE:To reduce an area of an electrical connection region by providing a conductive layer which fills a trench formed in a semiconductor substrate so as to come into contact with the electrical connection region and which is extended to the outside of the trench. CONSTITUTION:An electrical connection region 21 and a trench 23 are brought into contact with each other; a conductive layer 17 fills the trench 23; as a result, the conductive layer 37 comes into contact with the electrical connection region 21 in a self-aligned manner. Consequently, it is not required to secure, in the electrical connection region 21, an area corresponding to a positioning region of the conductive layer 17; it is possible to reduce an area by this portion. Since the conductive layer 17 and the electrical connection region 21 are brought into contact with each other at a side face of the trench 23, it is possible to reduce a plane area corresponding to this contact area. Thereby, an area of the electrical connection region can be reduced.

公开(公告)号：JPH031533A

公开(公告)日：1991-01-08

申请号：JP13487089

申请日：1989-05-29

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L21/302 ,  H01L21/3065

Abstract: PURPOSE:To automatically remove a middle layer before etching of an aluminum-based thereby obtaining an etching method which can despense with a special process of removing a middle layer by forming a protective film, a lower resist layer, a middle layer, and an upper resist layer in order on an aluminum--based material film, and performing etching with these as masks. CONSTITUTION:If alpha-S is used as materials for a middle layer 23 and a protective film 21, while the protective film 21 is being anisotropically etched, for example, at a low temperature with a lower resist pattern 22P as a mask, it is etched, and the surface of the resist material of the low resist pattern 22P is exposed, and when etching an Al film being an aluminum-based material film 1, the substance decomposed form the resist protects the side wall of Al, whereby anisotropic etching of Al becomes possible. Moreover, after polysilicon or alpha-Si of the protective film 21 is etched off, even if the polysilicon or the alpha-Si as a middle layer pattern 23P remains, it can be removed by continuing the etching until it disappears.

公开(公告)号：JPH02148864A

公开(公告)日：1990-06-07

申请号：JP30328788

申请日：1988-11-30

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L21/76 ,  H01L21/265 ,  H01L27/08

Abstract: PURPOSE:To prevent the formation of a parasitic channel along the sidewall of a groove and to prevent the generation of leaking currents by forming the groove in a semiconductor substrate, doping impurities into the upper part of the side wall of said groove, and forming a channel stopping region. CONSTITUTION:An n type channel stopping region 13 is formed on the sidewall of a deep groove 3 on the side of a p-type well 2. Even if fixed positive charge is present at the interface of SiO2/Si in the groove 3, the formation of a parasitic n-type channel is prevented at the part of said channel stopping region 13. Therefore, even if the parasitic-type channel is supposed to the formed along the sidewall at a part other than the channel stopping region 13 of the deep groove 3, the channel is discontinued at the part of the channel stopping region 13. Thus, the generation of leaking currents between a source region 9 and a drain region 10 and the generation of leaking currents between the source and drain regions 9 and 10 and an n-type Si substrate 1 through said parasitic n-type channel can be prevented. In this way, defects in CMOSLSI due to the leaking currents can be prevented.