公开(公告)号：US12051742B1

公开(公告)日：2024-07-30

申请号：US18577714

申请日：2022-12-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Long Zhang ,  Weifeng Sun ,  Siyang Liu ,  Jie Ma ,  Peigang Liu ,  Longxing Shi

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L29/207 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

Abstract: An enhancement-mode N-channel and P-channel GaN device integration structure comprises a substrate, wherein an Al—N nucleating layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer are sequentially arranged on the substrate, and the AlGaN barrier layer and the GaN channel layer are divided by an isolation layer; a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer, a first GaN isolation layer and a first P+-GaN layer are sequentially arranged on the first P-GaN layer, a first source, a first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-channel device is arranged on the other side of the isolation layer.

公开(公告)号：US12027516B1

公开(公告)日：2024-07-02

申请号：US18568277

申请日：2022-12-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Siyang Liu ,  Sheng Li ,  Chi Zhang ,  Weifeng Sun ,  Mengli Liu ,  Yanfeng Ma ,  Longxing Shi

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/7787

Abstract: A GaN power semiconductor device integrated with a self-feedback gate control structure comprises a substrate, a buffer layer, a channel layer and a barrier layer. A gate control area is formed by a first metal source electrode, a first P-type GaN cap layer, a first metal gate electrode, a first metal drain electrode, a second P-type GaN cap layer and a second metal gate electrode. An active working area is formed by the first metal source electrode, a third P-type GaN cap layer, a third metal gate electrode, a second metal drain electrode, the second P-type GaN cap layer and a second metal source electrode. The overall gate leaking current of the device is regulated by the gate control area, the integration level is high, the parasitic effect is small, and the charge-storage effect can be effectively relieved, thus improving the threshold stability of the device.

公开(公告)号：US11894458B2

公开(公告)日：2024-02-06

申请号：US17762206

申请日：2020-09-25

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jiaxing Wei ,  Qichao Wang ,  Kui Xiao ,  Dejin Wang ,  Li Lu ,  Ling Yang ,  Ran Ye ,  Siyang Liu ,  Weifeng Sun ,  Longxing Shi

IPC: H01L29/78

CPC classification number: H01L29/7825

Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

公开(公告)号：US11651766B2

公开(公告)日：2023-05-16

申请号：US17181908

申请日：2021-02-22

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei Shan ,  Lixuan Zhu ,  Jun Yang ,  Longxing Shi

IPC: G10L15/02 ,  G06F17/14 ,  G10L25/24

CPC classification number: G10L15/02 ,  G06F17/142 ,  G10L25/24

Abstract: The present invention discloses an ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial fast Fourier transform (FFT), and belongs to the technical field of computation, calculation or counting. The circuit is oriented to the field of intelligence, and is integrally composed of a pre-process module, a windowing module, a Fourier transform module, a Mel filtering module, an adjacent frame merging module, a discrete cosine transform (DCT) module and other modules by optimizing the architecture of a Mel-frequency Cepstral Coefficients (MFCC) algorithm. Large-scale storage caused by framing is avoided in a non-overlapping framing mode, storage contained in the MFCC algorithm is further reduced, and the circuit area and the power consumption are greatly reduced. An FFT algorithm in the feature extraction circuit adopts a serial pipeline mode to process data, makes full use of the characteristics of serial inflow of audio data, and further reduces the storage area and operations of the circuit.

公开(公告)号：US11515395B2

公开(公告)日：2022-11-29

申请号：US17624336

申请日：2020-09-25

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD

Inventor： Siyang Liu ,  Ningbo Li ,  Dejin Wang ,  Kui Xiao ,  Chi Zhang ,  Sheng Li ,  Xinyi Tao ,  Weifeng Sun ,  Longxing Shi

IPC: H01L29/872 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/861

Abstract: A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.

公开(公告)号：US11367785B2

公开(公告)日：2022-06-21

申请号：US17606216

申请日：2020-03-31

Applicant: SOUTHEAST UNIVERSITY

Inventor： Jing Zhu ,  Ankang Li ,  Long Zhang ,  Weifeng Sun ,  Shengli Lu ,  Longxing Shi

IPC: H01L29/73 ,  H01L29/739 ,  H01L29/10

Abstract: A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer. The polysilicon gate includes a first gate located above the surface of the P-type body region and a second gate located above the pinch-off region and the N-type drift region. The first gate is connected to a first gate resistor, and the second gate is connected to a second gate resistor.

公开(公告)号：US11081967B2

公开(公告)日：2021-08-03

申请号：US16617508

申请日：2018-09-28

Applicant: SOUTHEAST UNIVERSITY

Inventor： Qinsong Qian ,  Shengyou Xu ,  Qi Liu ,  Weifeng Sun ,  Shengli Lu ,  Longxing Shi

IPC: H02M3/335 ,  H02M1/08 ,  H02M1/00

Abstract: The invention discloses a self-adaptive synchronous rectification control system and a self-adaptive synchronous rectification control method of an active clamp flyback converter. The control system comprises a sampling and signal processing circuit, a control circuit with a microcontroller as a core and a gate driver. According to the control method, a switching-on state, an early switching-off state, a late switching-off state and an exact switching-off state of a secondary synchronous rectifier of the active clamp flyback converter can be directly detected, and the synchronous rectifier and a switching-on time of the synchronous rectifier in next cycle can be controlled according to a detection result. After several cycles of self-adaptive control, the synchronous rectifier enters the exact switching-on state, thus avoiding oscillation of an output waveform of the active clamp flyback converter.

公开(公告)号：US09236115B2

公开(公告)日：2016-01-12

申请号：US14369651

申请日：2012-12-27

Applicant: SOUTHEAST UNIVERSITY

Inventor： Na Bai ,  Longxing Shi ,  Jun Yang ,  Xinning Liu ,  Jiafeng Zhu ,  Yue Feng ,  Cai Gong ,  Fei Pan ,  Hong Chang ,  Yifeng Deng ,  Yuan Chen ,  Yingcheng Xia

IPC: G11C11/419 ,  G11C11/417 ,  H01L27/11 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/417 ,  H01L27/1104

Abstract: A circuit for improving process robustness of sub-threshold SRAM memory cells serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to PMOS transistors of the sub-threshold SRAM memory cell and substrate of PMOS transistors in the circuit. The circuit includes a detection circuit for threshold voltages of the PMOS transistors and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS transistors in the sub-threshold SRAM memory cell and the PMOS transistors in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS and NMOS transistor resulted from process fluctuations and thereby regulates the threshold voltages of the PMOS transistors, so that the threshold voltages of the PMOS and NMOS transistors match. The circuit improves the noise margin of sub-threshold SRAM memory cells and the process robustness of sub-threshold SRAM memory cells.

Abstract translation: 用于提高子阈值SRAM存储单元的工艺稳健性的电路用作子阈值SRAM存储单元的辅助电路。 电路的输出端连接到子阈值SRAM存储单元的PMOS晶体管和电路中PMOS晶体管的衬底。 该电路包括用于PMOS晶体管的阈值电压的检测电路和差分输入和单端输出放大器。 该电路通过检测来自过程波动的PMOS和NMOS晶体管的阈值电压波动，以自适应的方式改变子阈值SRAM存储单元中的PMOS晶体管的衬底电压和电路中的PMOS晶体管，从而调节阈值 PMOS晶体管的电压，使得PMOS和NMOS晶体管的阈值电压匹配。 该电路提高了亚阈值SRAM存储单元的噪声容限和子阈值SRAM存储单元的工艺稳健性。

公开(公告)号：US08922265B1

公开(公告)日：2014-12-30

申请号：US14369652

申请日：2012-12-27

Applicant: Southeast University

Inventor： Na Bai ,  Longxing Shi ,  Jun Yang ,  Xinning Liu ,  Jiafeng Zhu ,  Yue Feng ,  Cai Gong ,  Fei Pan ,  Hong Chang ,  Yifeng Deng ,  Yuan Chen ,  Yingcheng Xia

IPC: H03L5/00 ,  H03K3/013 ,  H03K3/012

CPC classification number: H03K3/013 ,  G11C11/417 ,  G11C11/419 ,  H03K3/012

Abstract: Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals. The current compensation circuit can be used for an SRAM bit line leakage current compensation circuit, because the existence of a large leakage current on the SRAM bit line leads to the decreasing of a voltage difference between two ends of the bit line, resulting in that a subsequent circuit cannot correctly identify a signal.

Abstract translation: 公开了一种噪声电流补偿电路。 该电路设有两个输入和输出端子A和B，以及两个控制端子CON和CONF。 控制端子控制补偿电路的工作模式（工作状态和预充电状态）。 补偿电路由7个PMOS晶体管和8个NMOS晶体管组成。 在正常工作状态下，通过检测原始电路中两根信号线的电位变化率的变化，噪声电流补偿电路自动使缓慢放电的原电路的一端缓慢放电，使一端 原始电路快速放电以更快地放电信号，从而消除噪声电流对电路的影响，并为后续电路信号的正确识别提供帮助。 电流补偿电路可以用于SRAM位线漏电流补偿电路，因为SRAM位线上存在大的漏电流导致位线两端之间的电压差减小，导致 后续电路无法正确识别信号。

公开(公告)号：US12107167B2

公开(公告)日：2024-10-01

申请号：US17762929

申请日：2021-01-20

Applicant: SOUTHEAST UNIVERSITY

Inventor： Siyang Liu ,  Weifeng Sun ,  Chi Zhang ,  Shuxuan Xin ,  Shen Li ,  Le Qian ,  Chen Ge ,  Longxing Shi

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/778 ,  H01L29/812

CPC classification number: H01L29/7851 ,  H01L29/1095 ,  H01L29/778 ,  H01L29/8122

Abstract: The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the metal gate electrode and the source metal electrode only exist in the cell region, and the passivation layer of the terminal region extends upwards and is wrapped outside the channel layer. This structure can increase a threshold voltage of the device, improve the blocking characteristics of the device and reduce the size of a gate capacitance.