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    11.
    发明专利
    未知

    公开(公告)号：DE69530748D1

    公开(公告)日：2003-06-18

    申请号：DE69530748

    申请日：1995-12-20

    Applicant: ST MICROELECTRONICS INC

    Inventor： MCCLURE DAVID C

    IPC: G05F3/24 ,  G05F1/46 ,  G05F1/56 ,  H03F3/34 ,  H03F3/343 ,  H03F3/347 ,  H03F3/45

    Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage, or for generating a reference voltage for application to a circuit other than an output buffer and that demands sink current, is also disclosed. The voltage reference and regulator is based on a current mirror, in which the sum of the current in the current mirror is controlled by a bias current source which may be dynamically controlled within the operating cycle or programmed by way of fuses. A sink current path circuit, according to various alternatives, is disclosed as providing an additional sink current path in the event that the limited output high voltage, or reference voltage, exceeds the desired level.

    12.
    发明专利
    未知

    公开(公告)号：DE69523009T2

    公开(公告)日：2002-06-06

    申请号：DE69523009

    申请日：1995-10-27

    Applicant: ST MICROELECTRONICS INC

    Inventor： MCCLURE DAVID C

    IPC: G11C11/401 ,  G11C29/00 ,  G11C29/06 ,  G11C29/34 ,  G11C29/50

    Abstract: A plurality of bit lines is arranged in columns and grouped into a first set of bit lines and a second set of bit lines. Each bit line in the first set of bit lines alternates with each bit line in the second set of bit lines. First switching means electrically connects the first set of bit lines to a first voltage level and, simultaneously, second switching means connects the second set of bit lines to a second voltage level. This permits a bit line stress test that will reveal defects or failures in a memory chip.

    13.
    发明专利
    未知

    公开(公告)号：DE69521484T2

    公开(公告)日：2002-05-16

    申请号：DE69521484

    申请日：1995-11-28

    Applicant: ST MICROELECTRONICS INC

    Inventor： MCCLURE DAVID C

    IPC: G05F3/24 ,  G05F1/46 ,  G05F1/56 ,  H03F3/34 ,  H03F3/343 ,  H03F3/347 ,  H03F3/45

    Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses. An offset compensating current source adds current into the reference leg of the current mirror to eliminate the development of an offset voltage in the current mirror, and the limited output high voltage is shifted by the threshold voltage of the pull-up drive transistor by way of a threshold shift circuit.

    15.
    发明专利
    未知

    公开(公告)号：DE69515621T2

    公开(公告)日：2000-07-06

    申请号：DE69515621

    申请日：1995-11-28

    Applicant: ST MICROELECTRONICS INC

    Inventor： MCCLURE DAVID C

    IPC: G05F3/26 ,  H03K19/0185 ,  H03K19/00

    Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver (20) drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer (21), such that the drive signal applied to the gate of the pull-up transistor (32) in the output driver (20) is limited by the limited output high voltage applied to the output buffer (21). A voltage reference and regulator circuit (24) for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source (26), which may be dynamically controlled within the operating cycle or programmed by way of fuses. An offset compensating current source (28) adds current into the reference leg of the current mirror to eliminate the development of an offset voltage in the current mirror, and the limited output high voltage is shifted by the threshold voltage of the pull-up drive transistor (32) by way of a threshold shift circuit (30).

    19.
    发明专利
    未知

    公开(公告)号：DE69529557T2

    公开(公告)日：2003-12-11

    申请号：DE69529557

    申请日：1995-11-21

    Applicant: ST MICROELECTRONICS INC

    Inventor： MCCLURE DAVID C ,  TEEL THOMAS A

    IPC: H03K17/14 ,  G05F3/20 ,  H03F1/30 ,  H03F3/16 ,  H03F3/45 ,  H03K17/687 ,  H03K19/00 ,  H03K19/0175

    Abstract: A bias circuit for generating a bias voltage over variations in the power supply voltage and over process parameters is disclosed. The bias circuit utilizes a voltage divider to generate a divided voltage based on the power supply value. The divided voltage is applied to the gate of a modulating transistor (biased in saturation) in a current mirror, which controls a current applied to a linear load device biased in the linear region. The voltage across the load device determines the bias voltage. Variations in the power supply voltage are thus reflected in the bias voltage, such that the gate-to-source voltage of the series transistor is constant over variations in power supply voltage. Variations in process parameters that produce different transistor current drive characteristics are reflected in a variations of the bias voltage produced by the linear load device. The bias circuit may control the slew rate of an output driver, may control the propagation delay through a delay element, and be used to control the duration of a pulse produced by a pulse generating circuit.

    20.
    发明专利
    未知

    公开(公告)号：DE69626067D1

    公开(公告)日：2003-03-13

    申请号：DE69626067

    申请日：1996-05-15

    Applicant: ST MICROELECTRONICS INC

    Inventor： MCCLURE DAVID C

    IPC: G11C7/12 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

    Abstract: A circuit biases an associated pair of bit lines. A fuse is coupled between a biasing voltage and a node. A first load is coupled between the node and a first of the bit lines. A second load is coupled between the node and a second of the bit lines.

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