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公开(公告)号：JP2003249074A
公开(公告)日：2003-09-05
申请号：JP2003023822
申请日：2003-01-31
Applicant: ST MICROELECTRONICS INC
Inventor： MCCLURE DAVID C
Abstract: PROBLEM TO BE SOLVED: To provide an improved circuit and a method for testing deterioration of a ferroelectric memory cell. SOLUTION: A circuit and a method for testing a memory cell of a ferroelectric memory device equipped with an array consisting of ferroelectric memory is provided. The test circuit is coupled to the bit lines, the determines selectively the voltage levels appearing on the bit lines based on a measured current level and supplies externally an electrical signal representative of the sensed voltage levels to the ferroelectric memory device. In this way, ferroelectric memory cells exhibiting degraded performance is identified. COPYRIGHT: (C)2003,JPO
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公开(公告)号：JP2004005992A
公开(公告)日：2004-01-08
申请号：JP2003157166
申请日：2003-06-02
Applicant: ST MICROELECTRONICS INC
Inventor： MCCLURE DAVID C
Abstract: PROBLEM TO BE SOLVED: To provide a redundant circuit and a method which effectively replace at least one defective memory cell in a memory device. SOLUTION: The redundant circuit is provided with a redundant decoding circuit which selectively maintains an address of the defective memory cell in the memory device, receives an input address and generates an output signal having a value indicating whether or not the input address corresponds to the address of the defective memory cell. The redundant circuit is further provided with a plurality of redundant storage circuits for selectively maintaining a data value and a redundant control circuit which selectively and individually accesses the first one among the redundant storage circuits based on a value of the output signal of the redundant decoding circuit. COPYRIGHT: (C)2004,JPO
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公开(公告)号：JP2002123339A
公开(公告)日：2002-04-26
申请号：JP2001227734
申请日：2001-07-27
Applicant: ST MICROELECTRONICS INC
Inventor： MCCLURE DAVID C , YOUSSEF TOM
Abstract: PROBLEM TO BE SOLVED: To provide a technology for switching from a primary power source to a secondary power source without loosing data stored from a volatile element. SOLUTION: This integrated circuit has a forcible power source switching circuit which detects the supply level of the primary power source dropping below a predetermined threshold level. The switching circuit on the integrated circuit starts switching operation once the forcible power source switching circuit detects the supply level received from the primary power source dropping the predetermined threshold level. The detection by the forcible power source switching circuit can be generated at a signal level having faster transition than a specific negative variation rate. This integrated circuit can be built in an arbitrary system equipped with a memory or a volatile element such as a clock.
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公开(公告)号：DE69529557D1
公开(公告)日：2003-03-13
申请号：DE69529557
申请日：1995-11-21
Applicant: ST MICROELECTRONICS INC
Inventor： MCCLURE DAVID C , TEEL THOMAS A
IPC: H03K17/14 , G05F3/20 , H03F1/30 , H03F3/16 , H03F3/45 , H03K17/687 , H03K19/00 , H03K19/0175
Abstract: A bias circuit for generating a bias voltage over variations in the power supply voltage and over process parameters is disclosed. The bias circuit utilizes a voltage divider to generate a divided voltage based on the power supply value. The divided voltage is applied to the gate of a modulating transistor (biased in saturation) in a current mirror, which controls a current applied to a linear load device biased in the linear region. The voltage across the load device determines the bias voltage. Variations in the power supply voltage are thus reflected in the bias voltage, such that the gate-to-source voltage of the series transistor is constant over variations in power supply voltage. Variations in process parameters that produce different transistor current drive characteristics are reflected in a variations of the bias voltage produced by the linear load device. The bias circuit may control the slew rate of an output driver, may control the propagation delay through a delay element, and be used to control the duration of a pulse produced by a pulse generating circuit.
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公开(公告)号：DE69525517T2
公开(公告)日：2002-09-12
申请号：DE69525517
申请日：1995-11-28
Applicant: ST MICROELECTRONICS INC
Inventor： MCCLURE DAVID C
IPC: H03K19/0175 , G05F1/46 , G11C11/407 , H03K19/0185 , H03K19/0948
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Patent Agency Ranking
公开(公告)号：DE69523547T2
公开(公告)日：2002-06-27
申请号：DE69523547
申请日：1995-11-28
Applicant: ST MICROELECTRONICS INC
Inventor： MCCLURE DAVID C
Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses. An offset compensating current source adds current into the reference leg of the current mirror to eliminate the development of an offset voltage in the current mirror, and the limited output high voltage is shifted by the threshold voltage of the pull-up drive transistor by way of a threshold shift circuit.
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公开(公告)号：DE69518616T2
公开(公告)日：2001-05-03
申请号：DE69518616
申请日：1995-11-28
Applicant: ST MICROELECTRONICS INC
Inventor： MCCLURE DAVID C
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公开(公告)号：DE69530748T2
公开(公告)日：2004-03-11
申请号：DE69530748
申请日：1995-12-20
Applicant: ST MICROELECTRONICS INC
Inventor： MCCLURE DAVID C
Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage, or for generating a reference voltage for application to a circuit other than an output buffer and that demands sink current, is also disclosed. The voltage reference and regulator is based on a current mirror, in which the sum of the current in the current mirror is controlled by a bias current source which may be dynamically controlled within the operating cycle or programmed by way of fuses. A sink current path circuit, according to various alternatives, is disclosed as providing an additional sink current path in the event that the limited output high voltage, or reference voltage, exceeds the desired level.
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公开(公告)号：DE69626067T2
公开(公告)日：2004-01-22
申请号：DE69626067
申请日：1996-05-15
Applicant: ST MICROELECTRONICS INC
Inventor： MCCLURE DAVID C
Abstract: A circuit biases an associated pair of bit lines. A fuse is coupled between a biasing voltage and a node. A first load is coupled between the node and a first of the bit lines. A second load is coupled between the node and a second of the bit lines.
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公开(公告)号：DE69523009D1
公开(公告)日：2001-11-08
申请号：DE69523009
申请日：1995-10-27
Applicant: ST MICROELECTRONICS INC
Inventor： MCCLURE DAVID C
IPC: G11C11/401 , G11C29/00 , G11C29/06 , G11C29/34 , G11C29/50
Abstract: A plurality of bit lines is arranged in columns and grouped into a first set of bit lines and a second set of bit lines. Each bit line in the first set of bit lines alternates with each bit line in the second set of bit lines. First switching means electrically connects the first set of bit lines to a first voltage level and, simultaneously, second switching means connects the second set of bit lines to a second voltage level. This permits a bit line stress test that will reveal defects or failures in a memory chip.
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