公开(公告)号：DE602006019426D1

公开(公告)日：2011-02-17

申请号：DE602006019426

申请日：2006-06-26

Applicant: ST MICROELECTRONICS NV

Inventor： BERENS FRIEDBERT

IPC: H04L27/26 ,  H04B1/10 ,  H04B1/69

公开(公告)号：DE60009052T2

公开(公告)日：2004-10-21

申请号：DE60009052

申请日：2000-07-21

Applicant: ST MICROELECTRONICS NV

Inventor： BERENS FRIEDBERT

IPC: H04B1/707

Abstract: The Rake receiver uses a delayed version of the received sequence and a delayed version of scrambling code. The flexible hardware structure of the time-aligning and descrambling unit (DSU) comprises at least two delay chains (DCH1, DCH2A) and one multiplier (MTM). By controlling two multiplexers (MUX1, MUX2), the delayed versions of the received sequence can be multiplied with an arbitrary scrambling code having an arbitrary phase. During one chip period, for each path to be processed, one multiplication is performed.