公开(公告)号：FR2823010A1

公开(公告)日：2002-10-04

申请号：FR0104437

申请日：2001-04-02

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JOSSE EMMANUEL

IPC: H01L21/336 ,  H01L29/165 ,  H01L29/78

Abstract: Production of a vertical transistor having an insulated gate with four-channel conduction comprises forming a vertical semiconductor column on a semiconductor substrate, and forming a dielectrically insulated semiconductor gate on the sides of the column and on the upper surface of the substrate. Formation of the column (PIL) comprises forming a first semiconductor column on the substrate, and forming a cavity in the primary column. Formation of the insulated gate comprises coating the internal walls of the cavity with a dielectric insulating material and filling the insulated cavity with gate material (14), so as to form, between the part of the insulated gate located in the cavity and the part of the insulated grid located on the sides of the column, two semiconductor connection regions (PL1, PL2) extending between the source and the drain of the transistor. An Independent claim is given for an integrated circuit comprising the vertical transistor.