公开(公告)号：US20230260835A1

公开(公告)日：2023-08-17

申请号：US18109569

申请日：2023-02-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Pascal FORNARA

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/76858 ,  H01L21/76883 ,  H01L21/76844 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266

Abstract: A method of manufacturing a contact on a semiconductor region includes a step of forming a stack of layers on lateral walls and at a bottom of an orifice (aligned with the semiconductor region) crossing a dielectric region along a longitudinal direction. The step of forming step is carried out from a first surface of the dielectric region and includes forming a polysilicon layer and a layer of a first metal in contact with the polysilicon layer. The first metal is preferably a metal selected from the group of transition metals and is well suited to forming with the polysilicon layer a metal silicide. The method further includes a step of performing thermal anneal causing a reaction between the first metal and the polysilicon layer to produce a layer of metal silicide. At least a portion of that layer of metal silicide extends in the longitudinal direction of the orifice.

公开(公告)号：US20220005960A1

公开(公告)日：2022-01-06

申请号：US17366585

申请日：2021-07-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Brice ARRAZAT ,  Julien DELALLEAU ,  Joel METZ

IPC: H01L29/94 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11524 ,  H01L49/02 ,  H01L21/28 ,  H01L21/265

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

公开(公告)号：US20200160916A1

公开(公告)日：2020-05-21

申请号：US16747995

申请日：2020-01-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Christian RIVERO

IPC: G11C16/22 ,  G06F21/87 ,  H01L29/78 ,  H01L27/115 ,  H01L23/00 ,  H01L21/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/74 ,  H01L21/311

Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.

公开(公告)号：US20190103369A1

公开(公告)日：2019-04-04

申请号：US16208253

申请日：2018-12-03

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Pascal FORNARA ,  Guilhem BOUTON ,  Mathieu LISART

IPC: H01L23/00 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L21/768 ,  H01L23/58 ,  H01L21/8234

Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.

公开(公告)号：US20190043814A1

公开(公告)日：2019-02-07

申请号：US16051680

申请日：2018-08-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI ,  Christian RIVERO ,  Quentin HUBERT

IPC: H01L23/00 ,  H01L27/02 ,  G06F21/75

Abstract: An integrated electronic circuit includes a semiconductor substrate with a semiconductor well that is isolated by a buried semiconductor region located under the semiconductor well. A vertical MOS transistor formed in the semiconductor well includes a source-drain region provided by the buried semiconductor region. Backside thinning of the semiconductor substrate is detected by biasing the vertical MOS transistor into an on condition to supply a current and then comparing that current to a threshold. Current less than a threshold is indicative that the semiconductor substrate has been thinned from the backside.

公开(公告)号：US20230327028A1

公开(公告)日：2023-10-12

申请号：US18210155

申请日：2023-06-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Brice ARRAZAT ,  Julien DELALLEAU ,  Joel METZ

IPC: H01L29/94 ,  H01L21/28 ,  H01L21/265 ,  H01L29/423 ,  H01L29/788 ,  H10B41/35

CPC classification number: H01L29/945 ,  H01L29/40114 ,  H01L21/2652 ,  H01L28/91 ,  H01L29/4236 ,  H01L29/788 ,  H10B41/35

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

公开(公告)号：US20220123119A1

公开(公告)日：2022-04-21

申请号：US17504198

申请日：2021-10-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Philippe BOIVIN ,  Francois TAILLIET ,  Roberto SIMOLA

IPC: H01L29/423 ,  H01L27/11524 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: A memory transistor for a non-volatile memory cell includes a source region and a drain region implanted in a semiconductor substrate. The source region is spaced from the drain region. A double gate region for the memory transistor extends at least partly in depth in the semiconductor substrate between the source region and the drain region and further extends beyond this source region and this drain region. The memory cell further includes a selection transistor having a gate region that partially extends over the double gate region for the memory transistor.

公开(公告)号：US20200052073A1

公开(公告)日：2020-02-13

申请号：US16657409

申请日：2019-10-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem BOUTON ,  Pascal FORNARA ,  Christian RIVERO

IPC: H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L21/763 ,  H01L29/78 ,  H01L27/112

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US20190027581A1

公开(公告)日：2019-01-24

申请号：US16036453

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien DELALLEAU ,  Christian RIVERO

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423

Abstract: A MOS transistor is produced on and in an active zone and included a source region and a drain region. The active zone has a width measured transversely to a source-drain direction. A conductive gate region of the MOS transistor includes a central zone and, at a foot of the central zone, at least one stair that extends beyond the central zone along at least an entirety of the width of the active zone.

公开(公告)号：US20190027565A1

公开(公告)日：2019-01-24

申请号：US16037095

申请日：2018-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Guilhem BOUTON ,  Pascal FORNARA ,  Julien DELALLEAU

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/28

CPC classification number: H01L29/4238 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/78 ,  H01L29/7833

Abstract: A MOS transistor is produced on and in an active zone which includes a source region and a drain region. The active zone is surrounded by an insulating region. A conductive gate region of the transistor has two flanks which extend transversely to a source-drain direction, and the conductive gate region overlaps two opposite edges of the active zone act overlap zones. The conductive gate region includes, at a location of at least one overlap zone, at least one conductive tag which projects from at least one flank at a foot of the conductive gate region. The conductive tag covers a part of the active zone and a part of the insulating region.