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    Wide voltage range high performance sense amplifier
    11.
    发明授权
    Wide voltage range high performance sense amplifier 有权
    宽电压范围高性能读出放大器

    公开(公告)号：US09177637B1

    公开(公告)日：2015-11-03

    申请号：US14472166

    申请日：2014-08-28

    Applicant: STMicroelectronics International N.V.

    Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

    IPC: G11C11/00 ,  G11C11/419 ,  G11C7/06

    CPC classification number: G11C11/419 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1048 ,  G11C2207/002

    Abstract: A dual rail SRAM array includes a plurality of columns of memory cells each coupled between two bit lines. A sense amplifier is coupled between each pair of bit lines. Capacitors are positioned between the sense amplifier outputs and the bit lines, thereby separating the sense amplifier from the bit lines. The memory cells are powered with an array supply voltage. The sense amplifier is powered with a peripheral supply voltage. During a read operation of the memory array, the bit lines are precharged to the array supply voltage. The sense amplifier is precharged to the peripheral supply voltage or to an intermediate voltage.

    Abstract translation: 双轨SRAM阵列包括多个存储单元列，每个存储单元分别耦合在两个位线之间。 读出放大器耦合在每对位线之间。 电容器位于感测放大器输出和位线之间，从而将读出放大器与位线分离。 存储单元由阵列电源电压供电。 读出放大器由周边电源供电。 在存储器阵列的读取操作期间，位线被预充电到阵列电源电压。 读出放大器被预充电到外围电源电压或中间电压。

    Memory with an assist determination controller and associated methods
    12.
    发明授权
    Memory with an assist determination controller and associated methods 有权
    具有辅助确定控制器和相关方法的存储器

    公开(公告)号：US08982651B2

    公开(公告)日：2015-03-17

    申请号：US13852222

    申请日：2013-03-28

    Applicant: STMicroelectronics International N.V.

    Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

    IPC: G11C7/00 ,  G11C7/02 ,  G11C7/06

    CPC classification number: G11C7/06 ,  G11C7/14 ,  G11C11/419 ,  G11C17/18

    Abstract: A memory includes an array of active memory cells arranged in rows and columns, and at least one dummy memory cell column adjacent the array of active memory cells. A sensing circuit is coupled to the at least one dummy memory cell column to sense at least one variation associated with the at least one dummy memory cell column. An assist circuit is coupled to the array of active memory cells. An assist determination controller is coupled to the sensing circuit to store a look-up table of output assist values corresponding to different variations associated with the at least one dummy memory cell column, to determine an output assist value from the look-up table based upon the at least sensed variation, and to operate the assist circuit based upon the determined output assist value.

    Abstract translation: 存储器包括以行和列布置的活动存储单元的阵列，以及与活动存储器单元阵列相邻的至少一个虚拟存储单元列。 感测电路耦合到所述至少一个虚拟存储器单元列以感测与所述至少一个虚拟存储器单元列相关联的至少一个变化。 辅助电路耦合到有源存储器单元阵列。 辅助确定控制器耦合到感测电路以存储对应于与至少一个虚拟存储器单元列相关联的不同变化的输出辅助值的查找表，以基于查找表来确定来自查找表的输出辅助值 至少感测到的变化，并且基于所确定的输出辅助值来操作辅助电路。

    Data-dependent pullup transistor supply and body bias voltage application for a static random access memory (SRAM) cell
    13.
    发明授权
    Data-dependent pullup transistor supply and body bias voltage application for a static random access memory (SRAM) cell 有权
    用于静态随机存取存储器（SRAM）单元的数据相关上拉晶体管电源和体偏置电压

    公开(公告)号：US08724374B1

    公开(公告)日：2014-05-13

    申请号：US13655160

    申请日：2012-10-18

    Applicant: STMicroelectronics International N.V.

    Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

    IPC: G11C7/00 ,  G11C7/12 ,  G11C11/00 ,  G11C5/14 ,  G11C11/41 ,  G11C11/4074 ,  G11C16/30

    CPC classification number: G11C7/00 ,  G11C5/146 ,  G11C11/4074 ,  G11C11/41 ,  G11C11/412 ,  G11C11/417 ,  G11C16/30

    Abstract: A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node.

    Abstract translation: 存储单元包括真实数据节点，真实上拉晶体管，补码数据节点和补码上拉晶体管。 真正的开关电路选择性地将第一或第二电源电压提供给真正的上拉晶体管的源极。 真正的偏置开关电路选择性地将第三或第四电源电压提供给真正的上拉晶体管的主体。 当将逻辑高数据值写入真实数据存储节点时，控制电路使真正的开关电路提供第二电源电压和真偏压开关电路来提供第三电源电压。 第二电源电压高于第一电源电压，第四电源电压高于第三电源电压。 当向补码数据存储节点写入逻辑高数据值时，相对于补码上拉晶体管执行类似的操作。

    Elements for in-memory compute
    15.
    发明授权
    Elements for in-memory compute 有权

    公开(公告)号：US11829730B2

    公开(公告)日：2023-11-28

    申请号：US17940654

    申请日：2022-09-08

    Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Nitin Chawla ,  Tanmoy Roy ,  Anuj Grover ,  Giuseppe Desoli

    IPC: G06F7/57 ,  G06F3/06 ,  G06N3/063

    CPC classification number: G06F7/57 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06N3/063

    Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

    DATA-DEPENDENT PULLUP TRANSISTOR SUPPLY AND BODY BIAS VOLTAGE APPLICATION FOR A STATIC RANDOM ACCESS MEMORY (SRAM) CELL
    18.
    发明申请
    DATA-DEPENDENT PULLUP TRANSISTOR SUPPLY AND BODY BIAS VOLTAGE APPLICATION FOR A STATIC RANDOM ACCESS MEMORY (SRAM) CELL 有权
    用于静态随机存取存储器（SRAM）单元的依赖数据依赖的抽头晶体管供应和体位偏置电压应用

    公开(公告)号：US20140112081A1

    公开(公告)日：2014-04-24

    申请号：US13655160

    申请日：2012-10-18

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

    IPC: G11C7/00

    CPC classification number: G11C7/00 ,  G11C5/146 ,  G11C11/4074 ,  G11C11/41 ,  G11C11/412 ,  G11C11/417 ,  G11C16/30

    Abstract: A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node.

    Abstract translation: 存储单元包括真实数据节点，真实上拉晶体管，补码数据节点和补码上拉晶体管。 真正的开关电路选择性地将第一或第二电源电压提供给真正的上拉晶体管的源极。 真正的偏置开关电路选择性地将第三或第四电源电压提供给真正的上拉晶体管的主体。 当将逻辑高数据值写入真实数据存储节点时，控制电路使真正的开关电路提供第二电源电压和真偏压开关电路来提供第三电源电压。 第二电源电压高于第一电源电压，第四电源电压高于第三电源电压。 当向补码数据存储节点写入逻辑高数据值时，相对于补码上拉晶体管执行类似的操作。

    Memory calibration device, system and method
    19.
    发明授权
    Memory calibration device, system and method 有权

    公开(公告)号：US11776650B2

    公开(公告)日：2023-10-03

    申请号：US17846578

    申请日：2022-06-22

    Applicant: STMicroelectronics International N.V.

    Inventor： Tanmoy Roy ,  Anuj Grover

    IPC: G11C29/36 ,  G11C29/10 ,  G11C29/44

    CPC classification number: G11C29/36 ,  G11C29/10 ,  G11C29/44 ,  G11C2029/3602 ,  G11C2207/2254

    Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values. The stored data values may be stored in an in-memory compute cluster of the memory array, such that operations on the stored data values include combining the multiple data values of the in-memory compute cluster with at least a portion of the generated calibration information as at least part of an in-memory compute operation for the in-memory compute cluster.

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