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公开(公告)号：US11474788B2
公开(公告)日：2022-10-18
申请号：US16890870
申请日：2020-06-02
Inventor： Nitin Chawla , Tanmoy Roy , Anuj Grover , Giuseppe Desoli
Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
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公开(公告)号：US11360667B2
公开(公告)日：2022-06-14
申请号：US17012501
申请日：2020-09-04
Inventor： Nitin Chawla , Giuseppe Desoli , Anuj Grover , Thomas Boesch , Surinder Pal Singh , Manuj Ayodhyawasi
Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.
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公开(公告)号：US12292780B2
公开(公告)日：2025-05-06
申请号：US18338950
申请日：2023-06-21
Inventor： Nitin Chawla , Anuj Grover , Giuseppe Desoli , Kedar Janardan Dhori , Thomas Boesch , Promod Kumar
IPC: G06F1/3287 , G05F3/24 , G06F1/3234 , G06F15/78 , G11C11/413
Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.
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公开(公告)号：US11829730B2
公开(公告)日：2023-11-28
申请号：US17940654
申请日：2022-09-08
Inventor： Nitin Chawla , Tanmoy Roy , Anuj Grover , Giuseppe Desoli
CPC classification number: G06F7/57 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06N3/063
Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
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公开(公告)号：US20210241806A1
公开(公告)日：2021-08-05
申请号：US17158875
申请日：2021-01-26
Inventor： Nitin CHAWLA , Thomas BOESCH , Anuj Grover , Surinder Pal SINGH , Giuseppe DESOLI
Abstract: A system includes a random access memory organized into individually addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.
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Patent Agency Ranking
公开(公告)号：US11836346B2
公开(公告)日：2023-12-05
申请号：US17742987
申请日：2022-05-12
Inventor： Nitin Chawla , Giuseppe Desoli , Anuj Grover , Thomas Boesch , Surinder Pal Singh , Manuj Ayodhyawasi
CPC classification number: G06F3/0604 , G06F3/0619 , G06F3/0655 , G06F3/0679 , G06N3/08
Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.
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公开(公告)号：US11823771B2
公开(公告)日：2023-11-21
申请号：US17158875
申请日：2021-01-26
Inventor： Nitin Chawla , Thomas Boesch , Anuj Grover , Surinder Pal Singh , Giuseppe Desoli
Abstract: A system includes a random access memory organized into individually addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.
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公开(公告)号：US11726543B2
公开(公告)日：2023-08-15
申请号：US17111373
申请日：2020-12-03
Inventor： Nitin Chawla , Anuj Grover , Giuseppe Desoli , Kedar Janardan Dhori , Thomas Boesch , Promod Kumar
IPC: G06F1/3234 , G05F3/24 , G06F1/3287 , G06F15/78 , G11C11/413 , G11C5/14 , G11C11/417 , G06F1/26
CPC classification number: G06F1/3275 , G05F3/24 , G06F1/3287 , G06F15/7821 , G11C11/413
Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.
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公开(公告)号：US11798615B2
公开(公告)日：2023-10-24
申请号：US17721956
申请日：2022-04-15
Applicant: STMicroelectronics International N.V.
Inventor： Anuj Grover , Tanmoy Roy
IPC: G11C11/408 , G11C5/02 , G11C11/4091 , G11C11/4096
CPC classification number: G11C11/4085 , G11C5/025 , G11C11/4091 , G11C11/4096
Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.
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公开(公告)号：US10277207B1
公开(公告)日：2019-04-30
申请号：US15892308
申请日：2018-02-08
Applicant: STMicroelectronics International N.V.
Inventor： Alok Kumar Tripathi , Amit Verma , Anuj Grover , Deepak Kumar Bihani , Tanmoy Roy , Tanuj Agrawal
IPC: H03K3/00 , H03K3/3562 , G11C11/412
Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.
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