公开(公告)号：US20250142862A1

公开(公告)日：2025-05-01

申请号：US18385137

申请日：2023-10-30

Applicant: STMicroelectronics International N.V.

Inventor： Giovanni GIORGINO ,  Maria Eloisa CASTAGNA ,  Virgil GUILLON ,  Cristina TRINGALI ,  Ferdinando IUCOLANO ,  Aurore CONSTANT

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/20 ,  H01L29/66

Abstract: Methods, systems, and apparatuses for normally-on GaN high electron mobility transistors (HEMT) integration on monolithic p-GaN integrated circuits (ICs) platforms are provided. In particular, the integrated circuit platforms may include both enhancement mode and depletion mode HEMT power devices in monolithically integrated p-GaN power ICs. Exemplary methods may include treating at least one of a plurality of p-GaN gates with an in-situ plasma treatment to deactivate Mg in the p-GaN gate treated and deplete this p-Gan gate of Mg. The depleted p-GaN gate may be the gate for the normally on HEMT in the IC. At least one of the p-GaN gates not exposed to the in-situ plasma pretreatment may be the gate of the normally off HEMT in the IC.

公开(公告)号：US20240313102A1

公开(公告)日：2024-09-19

申请号：US18596536

申请日：2024-03-05

Applicant: STMicroelectronics International N.V.

Inventor： Cristina MICCOLI ,  Ferdinando IUCOLANO ,  Cristina TRINGALI ,  Maria Eloisa CASTAGNA ,  Alessandro CHINI

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462

Abstract: An integrated power device includes a heterostructure, having a channel layer and a barrier layer, a source contact, a drain contact, and a gate region, arranged on the barrier layer between the source contact and the drain contact. An insulating field structure is arranged on the barrier layer between the gate region and the drain contact. A field plate extends over the insulating field structure. The insulating field structure includes a first dielectric region made of a first dielectric material on the barrier layer and a second dielectric region made of a second dielectric material, selectively etchable with respect to the first dielectric material on the first dielectric region. On a side of the insulating field structure towards the gate region, the field plate is in contact with the first dielectric region.