公开(公告)号：EP1239366B1

公开(公告)日：2006-03-08

申请号：EP01130835.0

申请日：2001-12-27

Applicant: STMicroelectronics S.r.l.

Inventor： Navoni, Loris Giuseppe ,  Borgatti, Michele ,  Cali, Lorenzo ,  Rolandi, Pierluigi

IPC: G06F9/445

CPC classification number: G06F8/61

公开(公告)号：EP1445704A1

公开(公告)日：2004-08-11

申请号：EP03425069.6

申请日：2003-02-06

Applicant: STMicroelectronics S.r.l.

Inventor： Pelliconi, Roberto ,  Gazzina, Christian ,  Borgatti, Michele

IPC: G06F13/40 ,  G06F13/42 ,  G06F15/17

CPC classification number: G06F13/42

Abstract: A method for synchronizing the data interchange in a semiconductor substrate integrated electronic circuit (1) is described, comprising a transmitter block (2) and a receiver block (3) connected through a communication network (4) comprising the steps of:

generating a data signal having a transmission period (T TR ) on a first line (5) that from the transmitter block (2) must be received by the receiver block (3);
generating on a second line (6) a congestion signal from the receiver block (3) to the transmitter block (2) when a congestion event of the receiver block (3) occurs in order to interrupt the data signal transmission,
characterized in that it generates on a third line (7) a synchro signal starting from the transmitter block (2), this synchro signal indicating to the receiver block that the data signal comprises a new datum, and in that the congestion signal interrupts also the synchro signal transmission when a congestion event of the receiver block (3) occurs.
An integrated electronic circuit being integrated on a semiconductor substrate is also described, comprising a transmitter block (2) and a receiver block (3) connected through a communication network (4), the communication network comprising a first line (5) for a data signal, a second line for a congestion signal, and a third line (7) for a synchro signal.
An architecture for manufacturing an integrated electronic circuit being integrated on a semiconductor substrate is also described, comprising a transmitter block (P; 2) and a receiver block (P; 3) connected through a communication network (Q; 4)

Abstract translation: 通过一个通信网络中的一种用于在半导体衬底集成电子电路同步数据交换方法（1）中描述，其包括一个发射器块（2）和一个接收器块（3）（4）连接，包括以下步骤：产生一个数据 具有（5）上从发送器块做了第一线的传输周期（TTR）信号（2）必须由接收器块（3）接收的; 产生上的第二线（6）从所述接收器块（3）向发送器块（2）当接收块的拥塞事件（3），以便中断所述数据信号的发送时，在特征的拥塞信号做了它 在第三行基因速率（7）从发射器块（2）启动一个同步信号，该同步信号指示所述接收器块没有所述数据信号包括一个新的日期，并在DASS模具拥塞信号中断，因此同步信号的传输时 （3）发生接收机块的拥塞事件。 的集成电子电路被集成在一个半导体衬底上被这样描述，其包括一个发射器块（2），并通过通信网络相连的接收块（3）（4），所述通信网络包括第一线（5 ）用于数据信号，对于拥塞信号的第二线，以及用于同步信号的第三线（7）。 制造集成电子电路的结构被集成在一个半导体衬底上被这样描述，其包括一个发射器块（P 2）和一个接收器块（P，3）通过通信网络连接（Q，4）

公开(公告)号：EP1239367A1

公开(公告)日：2002-09-11

申请号：EP01130838.4

申请日：2001-12-27

Applicant: STMicroelectronics S.r.l.

Inventor： Borgatti, Michele ,  Navoni, Loris Giuseppe ,  Rolandi, Pierluigi

IPC: G06F9/445

CPC classification number: G06F1/1632

Abstract: The invention relates to an electronic system with modular expansion of its functions, which is of a type comprising a portable host electronic device (1) associated with an expansion module (8) adapted for quick-connect engagement and disengagement in/from the portable device (1), characterized in that the module (8) comprises the following components:

a series of peripheral devices (16) adapted to serve different classes of functions;
a non-volatile memory (17) storing information that pertains to configuring the different functions in the module (8);
a re-configurable device (18) adapted to establish connections, implement functional portions, and control all the system components;
a control device (19) adapted to cooperate with the host device (1) in guiding the steps for re-configuring the whole system; and
a software algorithm adapted to instruct the system to reconfigure itself on which function and with which characteristics.

Abstract translation: 本发明涉及一种具有其功能的模块化扩展的电子系统，其类型包括与扩展模块（8）相关联的便携式主机电子设备（1），该扩展模块适于快速连接和/或从便携式设备脱离 （1），其特征在于，所述模块（8）包括以下部件：适于服务于不同功能类别的一系列外围设备（16） 存储涉及在所述模块（8）中配置不同功能的信息的非易失性存储器（17）。 适于建立连接，实现功能部分和控制所有系统组件的可重新配置的设备（18）; 控制装置（19），适于与所述主机装置（1）协作以引导用于重新配置整个系统的步骤; 以及一种软件算法，用于指示系统重新配置其功能及其特性。

公开(公告)号：EP1067558A1

公开(公告)日：2001-01-10

申请号：EP99830438.0

申请日：1999-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Dozza, Davide ,  Canegallo, Roberto ,  Borgatti, Michele

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/26

Abstract: It is described a new method to codify the data for the writing of non volatile memory cells (6) included in a memory array (3). The method provides the following steps succession:

a) data to be memorized are initially sent to a small memory cell matrix (15) which acts as buffer;
b) a control logic (9) regulates the data flow between an input/output circuitry (8) of said memory array (3) and such small memory cells matrix buffer (15) and it provides to send the data to be memorised to a coder / decoder block (18);
c) the codified / decodified information by said coder / decoder block (18) is sent to an elaborator (20) which calculates the distance between two successive data combinations;
d) said control logic (9) indicates to a writing logic (22) the completion of the codification operation of the data to be stored in the memory array (3);
e) said writing logic (22) effects the programming of the memory array (3) cells (6) on the basis of the result of the calculus effectuated by said elaborator (20).

Abstract translation: 描述了一种编码用于写入存储器阵列（3）中的非易失性存储器单元（6）的数据的新方法。 该方法提供以下步骤：a）要存储的数据最初发送到作为缓冲器的小型存储单元矩阵（15）; b）控制逻辑（9）调节所述存储器阵列（3）的输入/输出电路（8）与所述小型存储单元矩阵缓冲器（15）之间的数据流，并且其提供将待存储的数据发送到 编码器/解码器块（18）; c）所述编码器/解码器块（18）的编码/解码信息被发送到计算两个连续数据组合之间的距离的精细器（20）; d）所述控制逻辑（9）向写入逻辑（22）指示要存储在存储器阵列（3）中的数据的编码操作的完成; e）所述写入逻辑（22）基于由所述精细器（20）所执行的微积分的结果来影响存储器阵列（3）单元（6）的编程。