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    Method for compacting the erased threshold voltage distribution of flash memory devices during writing operations
    13.
    发明公开
    Method for compacting the erased threshold voltage distribution of flash memory devices during writing operations 有权
    一种用于阈值电压的变细处理在写入操作期间被擦除闪存单元

    公开(公告)号：EP1909290A1

    公开(公告)日：2008-04-09

    申请号：EP06119452.8

    申请日：2006-08-24

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Micheloni, Rino ,  Crippa, Luca ,  Ravasio, Roberto ,  Pio, Federico

    IPC: G11C16/34

    CPC classification number: G11C16/344

    Abstract: A method for operating a flash memory device ( 100 ) is proposed. The memory device includes a matrix of memory cells ( 110 ) each one having a programmable threshold voltage (V T ) defining a value stored in the memory cell. The method includes the steps of crasing a block ( 115 ) of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell (110 0e ) of the block for writing a target value; restoring the threshold voltage of a subset (110 0e ; 110 1o ) of the memory cells of the block to the compacting range, the subset consisting of the at least one first memory cell (110 0e ) and/or at least one second memory cell of the block (110 1o ) being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

    Abstract translation: 一种用于操作闪存器件（100）的方法，提出了 所述存储器装置包含存储单元的矩阵（110）每一个具有 - 定义存储在存储单元中的值的可编程阈值电压（V T）。 该方法包括crasing存储器单元的块（115），以及预定义的压实范围内压实块的存储器单元的阈值电压，worin压实的步骤的步骤包括：选择至少一个第一存储单元（110 0E）用于写入目标值的块的; 的子集的阈值电压（110 0E; 110 1O）恢复该块的存储器单元内的压实范围，所述子集由......组成所述至少一个第一存储单元（110奥斯特）和/或至少一个第二存储单元 块（110 1O）邻近所述至少一个第一存储单元的; 并至少部分地写入目标值到所述至少一个第一存储单元。

    Method of programming cells of a NAND memory device
    15.
    发明公开
    Method of programming cells of a NAND memory device 有权
    Verfahren zur Zellprogrammierung einer NAND-Speichervorrichtung

    公开(公告)号：EP1883076A1

    公开(公告)日：2008-01-30

    申请号：EP06425536.7

    申请日：2006-07-28

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Crippa, Luca ,  Ravasio, Roberto ,  Micheloni, Rino

    IPC: G11C16/10 ,  G11C11/56

    CPC classification number: G11C16/10 ,  G11C7/18 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427

    Abstract: The capacitive coupling between two adjacent bitlines of a NAND memory device is relevant and this may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them.
    According to the disclosed method, first the even (odd) bitlines that include cells not to be programmed (BLE ,...,BLE ) are biased with a first voltage for inhibiting them from being programmed, typically the supply voltage (VDD), while the even (odd) bitlines that include cells to be programmed are grounded. Successively, the adjacent odd (even) bitlines (BLO ,...,BLO ) are biased at the supply voltage (VDD) or at an auxiliary voltage, for boosting the bias voltage of the even (odd) bitlines above the supply voltage.
    With this expedient, the bias voltage of the even (odd) bitlines that include cells not to be programmed is boosted because of the relevant parasitic coupling capacitances between adjacent bitlines. Therefore, no dedicated charge pump generator is needed.

    Abstract translation: NAND存储器件的两个相邻位线之间的电容耦合是相关的，并且这可以用于提升不被编程的位线的电压，以便阻止对它们的编程操作。 根据所公开的方法，首先，包含不被编程的单元（BLE <1>，...，BLE ）的偶数（奇数）位线被用于阻止它们被编程的第一电压偏置，通常 电源电压（VDD），而包括要编程的单元的偶数（奇数）位线接地。 接着，相邻的奇数（偶数）位线（BLO <0>，...，BLO ）偏置在电源电压（VDD）或辅助电压，用于升压偶数（奇数） 位于电源电压以上。 通过这种方式，由于相邻位线之间的相关寄生耦合电容，包括不编程单元的偶数（奇数）位线的偏置电压会升高。 因此，不需要专用的电荷泵发电机。

    Page buffer for multi-level nand flash memories
    16.
    发明公开
    Page buffer for multi-level nand flash memories 审中-公开
    Seitenpufferfürmehrstufigen NAND-Flash-Speicher

    公开(公告)号：EP1870901A1

    公开(公告)日：2007-12-26

    申请号：EP06115809.3

    申请日：2006-06-21

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Crippa, Luca ,  Micheloni, Rino

    IPC: G11C11/56 ,  G11C7/10 ,  G11C16/24

    CPC classification number: G11C7/1021 ,  G11C7/1039 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621

    Abstract: A page buffer (130) comprised in an electrically programmable memory device (100) is provided. The memory device includes also a plurality of memory cells (110), a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell, and at least one read/program unit (205) having a coupling line (SO) operatively associable with selected memory cells. The read/program unit is adapted to at least temporarily store data bits read from or to be written into selected memory cells and comprises programming state change enabling means (230-1,230-2,252,254,256,258,272,274,276,278) for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential. The programming state change enabling means comprises reading means (256,258,260,230-2), receiving means (252,254,230-1), and combining means (272,274) activatable during a combining phase. The combining means includes a coupling electrical path between the reading means and the receiving means, said coupling electrical line being kept isolated from the coupling electrical path during said combining phase.

    Abstract translation: 提供包括在电可编程存储器件（100）中的页缓冲器（130）。 存储器件还包括多个存储器单元（110），对于每个存储器单元定义的多个不同的编程状态，对应于可存储在每个存储单元中的数据位数N> = 2，以及至少一个读/ 单元（205）具有与所选择的存储器单元可操作地相关联的耦合线（SO）。 读/写单元适于至少临时存储从或将被写入所选择的存储单元中的数据位，并且包括编程状态改变使能装置（230-1,230-2,252,254,256,258,272,274,276,278），用于选择性地启用所选存储器的编程状态的改变 通过使耦合线在程序使能电位和程序禁止电位之间采取一个单元。 编程状态改变使能装置包括读取装置（256,258,260,230-2），接收装置（252,254,230-1）以及在组合阶段可激活的组合装置（272,274）。 组合装置包括在读取装置和接收装置之间的耦合电路，所述耦合电线在所述组合阶段期间与耦合电路保持隔离。

    A circuit for retrieving data stored in semiconductor memory cells
    17.
    发明公开
    A circuit for retrieving data stored in semiconductor memory cells 审中-公开
    哈尔伯特·贝尔塞勒（Gespeicherten）大卫。

    公开(公告)号：EP1729302A1

    公开(公告)日：2006-12-06

    申请号：EP05104656.3

    申请日：2005-05-31

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Crippa, Luca ,  Ragone, Giancarlo ,  Sangalli, Miriam ,  Micheloni, Rino

    IPC: G11C11/56 ,  G11C16/28 ,  G11C16/30

    CPC classification number: G11C11/5642 ,  G11C7/04 ,  G11C16/30

    Abstract: A circuit comprises at least one memory cell ( 110 ) adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator ( 300 ) is provided for generating a voltage (Vo) to be supplied to the at least one memory cell ( 110 ) for retrieving the data stored therein, the voltage generator including first means ( 305 ) adapted to cause the generated voltage take a value in a set of target values including at least one target value (Vr-1,Vr-2,Vr-3,Vfy-1,Vfy-2,Vfy-3), corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means ( Mt,Rs,325, R1,R2,330 ) for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element ( Mt ) having said electrical characteristic.

    Abstract translation: 电路包括至少一个存储单元（110），其适于根据其电特性的值存储数据，其根据第一变化规律表现出与温度的变化性; 提供电压发生器（300），用于产生要提供给所述至少一个存储单元（110）的电压（Vo），用于检索存储在其中的数据，所述电压发生器包括第一装置（305），其适于使所产生的电压 在包含至少一个目标值（Vr-1，Vr-2，Vr-3，Vfy-1，Vfy-2，Vfy-3）的目标值集合中取值， 记忆单元 电压发生器包括用于使所产生的电压所采用的值根据规定的第二变化规律随温度变化的第二装置（Mt，Rs，325，R1，R2,330），该规定的第二变化规律利用具有所述电特性的补偿电路元件 。

    High-voltage switch with low output ripple for non-volatile floating-gate memories
    18.
    发明公开
    High-voltage switch with low output ripple for non-volatile floating-gate memories 有权
    具有在输出一个低纹波用于非易失性浮栅存储器的高压开关

    公开(公告)号：EP1724784A1

    公开(公告)日：2006-11-22

    申请号：EP05425347.1

    申请日：2005-05-20

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Ragone, Giancarlo ,  Crippa, Luca ,  Sangalli, Miriam ,  Micheloni, Rino

    IPC: G11C8/08 ,  G11C16/08 ,  H02M3/07 ,  H03K17/06

    CPC classification number: H02M3/073 ,  G11C5/145 ,  G11C8/08 ,  G11C16/08 ,  G11C16/12 ,  H02M2003/077 ,  H03K3/356104 ,  H03K17/063 ,  H03K17/6872 ,  H03K17/6874

    Abstract: A high-voltage switch (24) has a high-voltage input terminal (29), receiving a high voltage (HV), and an output terminal (31). A pass transistor (36), having a control terminal, is connected between the high-voltage input terminal (29) and the output terminal (31). The output of a voltage-multiplying circuit (40) of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit (40) is of a symmetrical type, has first and second charge-storage means (41, 42), receiving a clock signal (CK) of a periodic type, and has a first circuit branch (44, 48) and a second circuit branch (45, 49), which are symmetrical to one another and operate in phase opposition with respect to the clock signal (CK).

    Abstract translation: 的高电压开关（24）具有一个高电压输入端（29）接收高电压（HV），和输出端子（31）。 具有控制端子的导通晶体管（36），被连接在高电压输入端（29）和输出端子（31）之间。 电荷泵型的电压倍增电路（40）的输出被连接到控制终端。 电压倍增电路（40）是对称型，具有第一和第二电荷存储装置（41，42）接收周期性类型的时钟信号（CK），并具有第一电路支路（44，48 ）和第二电路支路（45，49），它们彼此对称和反相相对于所述时钟信号（CK）进行操作。

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