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    Method for compacting the erased threshold voltage distribution of flash memory devices during writing operations
    2.
    发明公开
    Method for compacting the erased threshold voltage distribution of flash memory devices during writing operations 有权
    一种用于阈值电压的变细处理在写入操作期间被擦除闪存单元

    公开(公告)号：EP1909290A1

    公开(公告)日：2008-04-09

    申请号：EP06119452.8

    申请日：2006-08-24

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Micheloni, Rino ,  Crippa, Luca ,  Ravasio, Roberto ,  Pio, Federico

    IPC: G11C16/34

    CPC classification number: G11C16/344

    Abstract: A method for operating a flash memory device ( 100 ) is proposed. The memory device includes a matrix of memory cells ( 110 ) each one having a programmable threshold voltage (V T ) defining a value stored in the memory cell. The method includes the steps of crasing a block ( 115 ) of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell (110 0e ) of the block for writing a target value; restoring the threshold voltage of a subset (110 0e ; 110 1o ) of the memory cells of the block to the compacting range, the subset consisting of the at least one first memory cell (110 0e ) and/or at least one second memory cell of the block (110 1o ) being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

    Abstract translation: 一种用于操作闪存器件（100）的方法，提出了 所述存储器装置包含存储单元的矩阵（110）每一个具有 - 定义存储在存储单元中的值的可编程阈值电压（V T）。 该方法包括crasing存储器单元的块（115），以及预定义的压实范围内压实块的存储器单元的阈值电压，worin压实的步骤的步骤包括：选择至少一个第一存储单元（110 0E）用于写入目标值的块的; 的子集的阈值电压（110 0E; 110 1O）恢复该块的存储器单元内的压实范围，所述子集由......组成所述至少一个第一存储单元（110奥斯特）和/或至少一个第二存储单元 块（110 1O）邻近所述至少一个第一存储单元的; 并至少部分地写入目标值到所述至少一个第一存储单元。

    Method of erasing a flash memory
    6.
    发明公开
    Method of erasing a flash memory 有权
    Löschverfahrenfüreinen Flash-Speicher

    公开(公告)号：EP1229550A1

    公开(公告)日：2002-08-07

    申请号：EP01830067.3

    申请日：2001-02-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pio, Federico

    IPC: G11C16/16

    CPC classification number: G11C16/16

    Abstract: A method (t1c-t9c) of erasing a flash memory (300) integrated in a chip of semiconductor material (175) and comprising at least one matrix (105) of cells (Mhk) with a plurality of rows and a plurality of columns made in at least one insulated body (165j), the cells of each row being connected to a corresponding word line (WLh); the method includes the step (t2c-t1c) of applying a single erasing pulse relative to a selected single one of the at least one body to a selected subset of the word lines for erasing the cells of each corresponding row made in the selected body with no intermediate check of the completion of the erasure.

    Abstract translation: 一种擦除集成在半导体材料（175）的芯片中并且包括至少一个具有多个行的单元格（Mhk）的矩阵（105）和多个列的多个列的闪速存储器（300）的方法（t1c-t9c） 在至少一个绝缘体（165j）中，每行的单元连接到对应的字线（WLh）; 该方法包括将相对于所选择的至少一个主体中的所选单个擦除脉冲施加到所选择的字线子集的步骤（t2c-t1c），以用于擦除在所选择的主体中形成的每个对应行的单元格， 没有中间检查完成擦除。

    An electrically modifiable, non-volatile, semiconductor memory which can keep a datum stored until an operation to modify the datum is completed
    7.
    发明公开
    An electrically modifiable, non-volatile, semiconductor memory which can keep a datum stored until an operation to modify the datum is completed 有权
    保持写入数据的电可修改非易失性半导体存储器，直到它们的重新编程完成

    公开(公告)号：EP1220229A1

    公开(公告)日：2002-07-03

    申请号：EP00830878.5

    申请日：2000-12-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Gastaldi, Roberto ,  Lo Giudice, Gianbattista ,  Pasotti, Marco ,  Pio, Federico

    IPC: G11C16/10

    CPC classification number: G11C16/102

    Abstract: An electrically-modifiable, non-volatile, semiconductor memory comprising a plurality of user memory locations which can be addressed individually from outside the memory in order to read and to modify user memory location, there is a corresponding pair of physical memory locations ((X1, Y1), (X2, Y2); WORDn) in the memory, which assume, alternatively, the functions of an active memory location and of a non-active memory location, the active memory location containing a previously-written datum and the non-active memory location being available for the writing of a new datum to replace the previously-written datum, so that, upon a request to replace the previous datum with the new datum, the previous datum is kept in the memory until the new datum has been written.

    Abstract translation: 的电可修改，非易失性半导体存储器包括可以单独地被寻址的存储器外，以便读取和修改用户的存储位置的用户存储器位置的复数，有一对相应的物理存储器位置（（X1 ，Y1），（X2，Y2）;在所述存储器中，其中假设，WORDn）可选地，有源存储器位置和一个非活性的存储器位置的功能，活性存储器位置包含先前写入的日期和非 -active存储单元是可用于新的日期的书面替换先前写的日期，使得在更换以前的日期与新日期的请求，先前的日期是保存在内存，直到新的日期有 被写入。

    Process for manufacturing a non-volatile memory device
    9.
    发明公开
    Process for manufacturing a non-volatile memory device 有权
    制造非易失性存储器件的过程

    公开(公告)号：EP1715491A2

    公开(公告)日：2006-10-25

    申请号：EP06012616.6

    申请日：1999-04-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Gomiero, Enrico ,  Pio, Federico ,  Zuliani, Paola

    IPC: G11C16/04

    CPC classification number: G11C16/12 ,  G11C16/0433 ,  G11C16/30

    Abstract: This invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organised by the byte in rows (WL) and columns (BL), each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line (CG) through a selection element of the byte switch type, and each cell being connected to a respective control column (BL) through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase. This is achieved by forming the bit switch element (20) inside a well (13) and the byte switch element (21) directly in the substrate.

    Abstract translation: 本发明涉及一种调整半导体非易失性存储器中的擦除/编程电压的方法。 存储器由具有浮动栅极，控制栅极和漏极和源极端子的存储器单元的至少一个矩阵形成，并且由行（WL）和列（BL）中的字节组织，每个字节包括一组 具有通过字节开关类型的选择元件彼此并联连接到公共控制线（CG）的各个控制栅极的单元，并且每个单元通过位开关的选择元件连接到相应的控制列（BL） 类型。 有利地，为存储单元的编程电压提供双重调整，由此擦除阶段期间的编程电压可以比写入阶段期间的编程电压更高。 这通过在阱（13）内形成位开关元件（20）并直接在衬底中形成字节开关元件（21）来实现。

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