Method and device for analog programming of non-volatile memory cells, in particular flash memory cells
    11.
    发明公开
    Method and device for analog programming of non-volatile memory cells, in particular flash memory cells 失效
    方法和装置用于非易失性存储单元的模拟编程,尤其是闪速存储器单元

    公开(公告)号:EP0877386A1

    公开(公告)日:1998-11-11

    申请号:EP97830216.4

    申请日:1997-05-09

    CPC classification number: G11C27/005

    Abstract: For each cell (1) to be programmed, the present threshold value (V o ) of the cell is determined; the desired threshold value (V TAR ) is acquired; the analog distance between the present threshold value and the desired threshold value is calculated; and a programming pulse (S) is then generated, the duration of which is proportional to the analog distance calculated. The programming and reading cycle is repeated until the desired threshold is reached. By this means a time saving is obtained, owing to the reduction of the number of intermediate reading steps. The method permits programming in parallel and simultaneously of a plurality of cells (1) of a memory array (2) which is connected to a single word line (5 1 ) and to different bit lines (4 1 - 4 N ), each with a programming pulse (S 1 - S N ) the duration of which is proportional to the analog distance calculated for the same cell. The programming process is thus very fast, owing to parallel application of the programming and the saving in the intermediate reading cycles.

    Abstract translation: 对于每个电池(1)要被编程,本阈值(VO)的单元的是确定性的矿洞; 所需的阈值(VTAR)被获取; 本阈值和阈值之间的模拟距离要的计算出; 并然后产生一编程脉冲(S),所有的持续时间成比例的计算值模拟距离。 重复编程和读取周期,直到达到所需的阈值。 通过这种方式一个省时的获得,由于中间步骤读取的数目的减少。 该方法允许在并行和同时单元的多个编程(1),其连接到一个单一的字线(51)和到不同的位线(41 - 4N)的存储器阵列(2)所有的,每一个编程脉冲 (S1 - SN)的所有的持续时间成比例的用于相同小区中计算出的模拟距离。 编程过程因此是非常快的,由于编程的并行应用和中间读周期节省。

    High-precision analog reading circuit for memory arrays, in particular flash analog memory arrays
    12.
    发明公开
    High-precision analog reading circuit for memory arrays, in particular flash analog memory arrays 失效
    HochpräzisionsanalogleseschaltkreisfürSpeichermatrizen,insbesonderefürFlash-Analogspeichermatrizen

    公开(公告)号:EP0872850A1

    公开(公告)日:1998-10-21

    申请号:EP97830172.9

    申请日:1997-04-14

    CPC classification number: G11C16/28 G11C27/005

    Abstract: An analog reading circuit (10) comprising a current mirror circuit (19) forcing two identical currents into a cell (2) to be read and into a reference cell (27) and an operational amplifier (31) having an inverting input connected to the drain terminal (13) of the cell (2) to be read, a non-inverting input connected to the drain terminal (28) of the reference cell (27) and an output connected to the gate terminal (30) of the reference cell. The reference cell (27) therefore forms part of a negative feedback loop which maintains the overdrive voltages of the cell (2) to be read and the reference cell (27) constant, irrespective of temperature variations. The reading circuit (10) is also of high precision and has a high reading speed.

    Abstract translation: 一种模拟读取电路(10),包括电流镜电路(19),将两个相同的电流强制进入待读取的单元(2)并进入参考单元(27);以及运算放大器(31),其具有与 要读取的单元(2)的漏极端子(13),连接到参考单元(27)的漏极端子(28)的非反相输入端和连接到参考单元(20)的栅极端子(30)的输出端 。 因此,参考单元(27)形成负反馈回路的一部分,其保持要读取的单元(2)的过驱动电压和参考单元(27)恒定,而与温度变化无关。 读取电路(10)也具有高精度且读取速度高的特点。

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