公开(公告)号：EP1091485A1

公开(公告)日：2001-04-11

申请号：EP99830632.8

申请日：1999-10-08

Applicant: STMicroelectronics S.r.l.

Inventor： Tomasini, Luciano ,  Guinea, Jesus

IPC: H03F3/30

CPC classification number: H03F3/3028 ,  H03F3/3023

Abstract: An input stage (315) for a buffer (300) with negative feedback, having an input terminal (310in), an output terminal (110int), a first (110v) and a second (110g) supply terminal, a biasing branch (Ipa-Ipb), a first (M1a-Mm1a) and a second (Mm1b-M1b) balancing branch each comprising an active transistor (M1a; M1b) for supplying, at the output terminal (110int), a current depending on the current difference in the first (M1a-Mm1a) and second (M1mb-M1b) balancing branches, the biasing branch (Ipa-Ipb) and the first (M1a-Mm1a) and second (Mm1b-M1b) balancing branches being connected in parallel between the first (110v) and second (110g) supply terminals, wherein the input terminal (310in) divides the biasing branch into two input branches (Ipa-Dina; Dinb-Ipb) each comprising a constant-current generator (Ipa; Ipb), each active transistor (M1a; M1b) being connected to a corresponding current generator (Ipa; Ipb) for receiving a control voltage (Vgs) correlated with a voltage at the terminals of the current generator (Ipa; Ipb).

Abstract translation: 具有负反馈的缓冲器（300）的输入级（315），具有输入端（310in），输出端（110int），第一（110v）和第二（110g）供电端，偏压分支 -Ipb），第一（M1a-Mm1a）和第二（Mm1b-M1b）平衡支路，每个支路包括有源晶体管（M1a; M1b），用于在输出端（110int）处提供取决于电流差 第一（M1a-Mm1a）和第二（M1mb-M1b）平衡分支，偏置分支（Ipa-Ipb）和第一（M1a-Mm1a）和第二（Mm1b-M1b）平衡分支并联连接在第一（ 110v）和第二（110g）电源端子，其中输入端子（310in）将偏置支路分成两个分别包括恒流发生器（Ipa; Ipb）的输入支路（Ipa-Dina; Dinb-Ipb），每个有源晶体管 （M1a; M1b）连接到相应的电流发生器（Ipa; Ipb），用于接收与端子上的电压相关的控制电压（Vgs） 当前发电机（Ipa; IPB）。

公开(公告)号：EP1075107A1

公开(公告)日：2001-02-07

申请号：EP99830518.9

申请日：1999-08-06

Applicant: STMicroelectronics S.r.l.

Inventor： Guinea, Jesus ,  Tomasini, Luciano

IPC: H04L7/033 ,  H03L7/081 ,  H03L7/07

CPC classification number: H04J3/0685 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

Abstract: A bidirectional synchronous interface for the reception of a first flow of digital data (RX, RXEQ) with a first coding from a communication channel (2a), and for the transmission on said communication channel (2b) of a second flow of digital data (TX) with said first coding in synchrony with a local timing signal (CK), comprises synchronization means (6, 8) for synchronizing the interface with the first flow of digital data (RX, RXEQ).
The synchronization means comprise first circuit means (8) fed by said local timing signal (CK) to generate, starting from said local timing signal (CK), a plurality of repetition timing signals (CK1-CKn) delayed from one another by fractions of a period, and second circuit means (6) fed by said first flow of digital data (RX, RXEQ) and by said plurality of repetition timing signals (CK1-CKn) suitable for determining, in said plurality, a pre-selected repetition timing signal (CKR) substantially in synchrony with the first flow of digital data (RX, RXEQ).

Abstract translation: 一种双向同步接口，用于接收来自通信信道（2a）的第一编码的第一数字数据流（RX，RXEQ），以及用于在所述通信信道（2b）上传输第二数字数据流（ TX）与本地定时信号（CK）同步地具有所述第一编码，包括用于使接口与第一数字数据流（RX，RXEQ）同步的同步装置（6,8）。 同步装置包括由本地定时信号（CK）馈送的第一电路装置（8），以从所述本地定时信号（CK）开始产生多个相互延迟的重复定时信号（CK1-CKn） 以及由所述第一数字数据流（RX，RXEQ）和所述多个重复定时信号（CK1-CKn）馈送的第二电路装置（6），所述多个重复定时信号适合于在所述多个中确定预先选择的重复定时 信号（CKR）基本上与第一数字数据流（RX，RXEQ）同步。