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    Synchronous switching circuit for data recovery
    1.
    发明公开
    Synchronous switching circuit for data recovery 审中-公开
    Synchroner Schalter zurDatenrückgewinnung

    公开(公告)号：EP1128594A1

    公开(公告)日：2001-08-29

    申请号：EP00830131.9

    申请日：2000-02-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Guinea, Jesus ,  Rutar, Massimiliano ,  Tomasini, Luciano

    IPC: H04L7/033 ,  H04L7/00 ,  H03L7/081 ,  H03L7/07

    CPC classification number: H03L7/07 ,  H03L7/0814 ,  H04L7/0083 ,  H04L7/0337

    Abstract: A switching circuit for switching an output (CKS) to one of a plurality of N input clock signals (CK1-CKN) which are delayed relative to one another comprises circuit means (31-316, 7) responding to a control (CNT) in order to enable the transmission, on the output signal (CKS), of a new signal (CK(i-1); CKi) of the plurality of input signals which is advanced or delayed relative to a current signal (CKi; CK(i-1)) of the plurality of input signals which is currently transmitted on the output signal (CKS), the circuit means (31-316, 7) enabling the transmission of the new signal (CK(i-1); CKi) before disabling the transmission of the current signal (CKi; CK(i-1)) on the output signal (CKS) so as to prevent the production of false signals during the switching of the output signal from one of the clock signals to another.

    Abstract translation: 用于将输出（CKS）切换为相对于彼此延迟的多个N个输入时钟信号（CK1-CKN）中的一个的切换电路包括响应于控制（CNT）的电路装置（31-316,77） 使得能够在输出信号（CKS）上传输相对于当前信号（CKi; CK（i（i））提前或延迟的多个输入信号的新信号（CK（i-1）; CKi） -1）），可以在输出信号（CKS）上发送的多个输入信号中，能够在新的信号（CK（i-1）; CKi）之前发送的电路装置（31-316,7） 禁止在输出信号（CKS）上传输当前信号（CKi; CK（i-1）），以防止在将输出信号从一个时钟信号切换到另一个时产生假信号。

    Improved delay locked loop circuit
    4.
    发明公开
    Improved delay locked loop circuit 有权
    VerbesserteVerzögerungsregelschleife

    公开(公告)号：EP1271786A1

    公开(公告)日：2003-01-02

    申请号：EP01830437.8

    申请日：2001-06-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Guinea, Jesus ,  Tomasini, Luciano

    IPC: H03L7/081

    CPC classification number: H03L7/0814

    Abstract: The present invention relates a circuit for generating a digital output signal (56) locked to a phase of an input signal (24), comprising a plurality of delay cells (42), a first register (31) containing a first value, a phase detector (26) and a control logic (25), which is characterized by comprising a plurality of flip - flop devices (37, ..., 38), wherein storing said first value, a second register (30) containing a second value, a plurality of adder nodes (33) adapted to sum in each of said delay cells (42) said second value with the content of said selected flip - flop device (37, ..., 38), being said delay cells (42) adapted to provide said digital output signal (56), said phase detector (26), receiving said input signal (24) and said digital output signal (56), adapted to detect the phase difference (27) between said input signal and said digital output signal (56), said control logic (25) adapted to control said first and second value in function of said phase difference (27).

    Abstract translation: 本发明涉及一种用于产生锁定到输入信号（24）的相位的数字输出信号（56）的电路，包括多个延迟单元（42），包含第一值的第一寄存器（31），相位 检测器（26）和控制逻辑（25），其特征在于包括多个触发器装置（37，...，38），其中存储所述第一值，第二寄存器（30）包含第二值 多个加法器节点（33），适于将每个所述延迟单元（42）中的所述第二值与所述选择的触发器件（37，...，38）的内容相加，作为所述延迟单元（42） ）适于提供所述数字输出信号（56），所述相位检测器（26）接收所述输入信号（24）和所述数字输出信号（56），适于检测所述输入信号和所述数字输出信号 数字输出信号（56），所述控制逻辑（25）适于根据所述相位差（27）来控制所述第一和第二值。

    Equaliser
    5.
    发明公开
    Equaliser 有权
    Entzerrer

    公开(公告)号：EP1154586A1

    公开(公告)日：2001-11-14

    申请号：EP00830343.0

    申请日：2000-05-12

    Applicant: STMicroelectronics S.r.l.

    Inventor： Guinea, Jesus ,  Tomasini, Luciano ,  Milanese, Carlo Maria

    IPC: H04B3/14 ,  H03H11/04

    CPC classification number: H03H11/1291 ,  H03H11/0422 ,  H04B3/145

    Abstract: The present invention refers to a method and to an equalizer circuit of signals transmitted on a line. In an embodiment the equaliser circuit of signals transmitted on a line having an attenuation comprising: an analogical adaptive filter (1) applied in series to said line comprises at least two transconductance filters having a bias current (Pc1-Pcn) each and to which it is associated at least one pole and at least one zero the position in frequency of which in the working band (B) is variable in response to said bias current (Pc1-Pcn); a retroaction circuit (3, 4, 5, 6, 7) applied to the output of said filter (1) able to vary said bias current (Pc1-Pcn); said bias current (Pc1-Pcn) varies at the varying of said attenuation of said line; characterised in that said at least two transconductance filters have said bias current of prefixed value; said bias current is made to vary at the increasing of said attenuation so that said at least one pole is moved toward the high frequencies; said bias current is made to vary at the increasing of said attenuation so that said at least a zero is moved toward the low frequencies.

    Abstract translation: 本发明涉及在一条线路上发送的信号的方法和均衡器电路。 在一个实施例中，在具有衰减的线路上传输的信号的均衡器电路包括：与所述线串联施加的模拟自适应滤波器（1），包括至少两个具有偏置电流（Pc1-Pcn）的跨导滤波器， 至少一个极点和至少一个零点，工作频带（B）的频率位置响应于所述偏置电流（Pc1-Pcn）是可变的; 施加到能够改变所述偏置电流（Pc1-Pcn）的所述滤波器（1）的输出的回溯电路（3,4,5,6,7）; 所述偏置电流（Pc1-Pcn）在所述线路的衰减变化时变化; 其特征在于，所述至少两个跨导滤波器具有所述预定值的偏置电流; 所述偏置电流在所述衰减的增加中变化，使得所述至少一个极向高频移动; 所述偏置电流在所述衰减的增加中变化，使得所述至少一个零向低频移动。

    A circuit for compensating for the difference between the Vgs voltages of two MOS transistors
    6.
    发明公开
    A circuit for compensating for the difference between the Vgs voltages of two MOS transistors 有权
    Eine Schaltung zur Kompensation der Differenz der Vgs-Spannungen zweier MOS-Transistoren

    公开(公告)号：EP1094599A1

    公开(公告)日：2001-04-25

    申请号：EP99830662.5

    申请日：1999-10-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Tomasini, Luciano ,  Guinea, Jesus

    IPC: H03F1/30 ,  H03F3/30

    CPC classification number: H03F1/301 ,  H03F3/3001

    Abstract: The difference between the Vgs voltages of a first MOS transistor (Mp) and a second MOS transistor (Mn) of an integrated circuit due to variations in the production process and/or to variations of other parameters is compensated by a circuit (10) comprising a third MOS transistor (Mp1) and a fourth MOS transistor (Mn1) which are of the same type as the first transistor (Mp) and the second transistor (Mn), respectively, and are formed in the same integrated circuit, means (VDD, Mp2, Mp3) for biasing the third transistor (Mp1) and the fourth transistor (Mn1), means (Mp4-Mp7) for measuring the difference between the Vgs voltages of the third transistor (Mp1) and the fourth transistor (Mn1), means (R1) for generating a compensation current (Io) which is a predetermined function of the difference measured, and means (Sp1-Sp3, Ro) for modifying the biasing of the first MOS transistor (Mp) and of the second MOS transistor (Mn) with the use of the compensation current (Io).

    Abstract translation: 由于制造过程的变化和/或其他参数的变化，集成电路的第一MOS晶体管（Mp）和第二MOS晶体管（Mn）的Vgs电压之间的差异由电路（10）补偿，包括 分别与第一晶体管（Mp）和第二晶体管（Mn）相同类型的第三MOS晶体管（Mp1）和第四MOS晶体管（Mn1），并形成在同一集成电路中， ，Mp2，Mp3），用于测量第三晶体管（Mp1）和第四晶体管（Mn1）的Vgs电压之间的差的装置（Mp4-Mp7），用于偏置第三晶体管（Mp1）和第四晶体管（Mn1） 用于产生作为测量差的预定函数的补偿电流（Io）的装置（R1），以及用于修改第一MOS晶体管（Mp）和第二MOS晶体管（Mp）的偏置的装置（Sp1-Sp3，Ro） Mn），使用补偿电流（Io）。

    A detector for detecting timing in a data flow
    7.
    发明公开
    A detector for detecting timing in a data flow 审中-公开
    Datenfluss ein Detektor zur Erfassung von Synchronisierung在einem Datenfluss

    公开(公告)号：EP1076435A1

    公开(公告)日：2001-02-14

    申请号：EP99830524.7

    申请日：1999-08-12

    Applicant: STMicroelectronics S.r.l.

    Inventor： Guinea, Jesus ,  Tomasini, Luciano

    IPC: H04L7/033 ,  H03L7/081 ,  H03L7/07

    CPC classification number: H03L7/0814 ,  H03L7/07 ,  H04L7/0337

    Abstract: A detector for detecting timing in a digital data flow (BK) with a bit-time equal to T and with a coding which provides, at the beginning of the bit-time T, for no transition or for a transition of a first type or a transition of a second type and, in the middle of the bit-time T, for no transition or for a transition of the first type, comprises first circuit means (2) for generating four local timing signals (Q1-Q4) which have periods substantially equal to the bit-time and are out of phase with one another by 1/4 period, and second circuit means (3) for sampling the four local timing signals (Q1-Q4) upon each transition of the first type in the data flow and for determining, on the basis of the sampled states of the four local timing signals (Q1-Q4), whether a pair of reference signals (Q1-Q3) which are out of phase by one half period, of the four local timing signals (Q1-Q4), is advanced or delayed relative to the timing of the data flow, and consequently controlling the first circuit means in a manner such as to delay or to advance the four local timing signals (Q1-Q4).

    Abstract translation: 一种用于以比特时间等于T的数字数据流（BK）中的定时检测和用于在比特时间T开始时提供无转换或第一类型的转换的编码的检测器， 第二类型的转换，并且在位时间T的中间，用于无转换或第一类型的转换，包括用于产生四个本地定时信号（Q1-Q4）的第一电路装置（2），其具有 周期基本上等于比特时间，并且彼此相差1/4周期;以及第二电路装置（3），用于在第一类型的每个转换中对四个本地定时信号（Q1-Q4）进行采样 数据流，并且根据四个本地定时信号（Q1-Q4）的采样状态，确定四个本地定时信号（Q1-Q4）相差一个半周期的一对参考信号（Q1-Q3） 定时信号（Q1-Q4）相对于数据流的定时被提前或延迟，因此控制第一个循环 uit意味着以延迟或推进四个本地定时信号（Q1-Q4）的方式。

    An improved delay-locked loop circuit
    10.
    发明公开
    An improved delay-locked loop circuit 有权
    VerbesserteVerzögerungsregelschleife

    公开(公告)号：EP1094608A1

    公开(公告)日：2001-04-25

    申请号：EP99830657.5

    申请日：1999-10-18

    Applicant: STMicroelectronics S.r.l.

    Inventor： Guinea, Jesus ,  Tomasini, Luciano ,  Maggio, Santo

    IPC: H03L7/081 ,  H03L7/091

    CPC classification number: H03L7/0812 ,  H03L7/091

    Abstract: A delay-locked loop circuit ("DLL") comprises a delay line (1) with a delay (Δt) which can be varied in a controlled manner in order to delay a periodic input signal (CKin) of period T, and circuit means (2, 7) for controlling the delay line (1) in order to lock the delay (Δt) to the period T.
    The delay line (1) supplies to the control circuit means (2, 7) a plurality of periodic signals (CK1-CKN) each delayed relative to the periodic input signal by a respective fraction of the delay (Δt), and the control circuit means (2, 7) comprise sequence-detector circuit means (2) which can periodically detect, in the delayed signals, characteristic sequences of digital values indicative of the delay (Δt) and, in dependence on the type of characteristic sequence, can bring about a reduction or an increase in the delay (Δt) for locking to the period T.

    Abstract translation: 延迟锁定环电路（“DLL”）包括具有延迟（DELTA t）的延迟线（1），其可以以受控的方式变化，以便延迟周期T的周期性输入信号（CKin），并且电路 用于控制延迟线（1）以便将延迟（DELTA t）锁定到周期T的装置（2,7）。延迟线（1）向控制电路装置（2,7）供应多个周期 信号（CK1-CKN）各自相对于周期性输入信号延迟相应的延迟分数（DELTA t），并且控制电路装置（2,7）包括顺序检测器电路装置（2） 在延迟信号中，指示延迟（DELTA t）的数字值的特征序列和根据特征序列的类型可以导致锁定到周期T的延迟（DELTA t）的减小或增加 。

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