公开(公告)号：EP0952455A1

公开(公告)日：1999-10-27

申请号：EP98830246.9

申请日：1998-04-23

Applicant: STMicroelectronics S.r.l.

Inventor： Bruccoleri, Melchiorre ,  Ottini, Daniele ,  Demicheli, Marco ,  Bollati, Giacomino

IPC: G01R19/04

CPC classification number: G01R19/22

Abstract: A full-wave rectifier for monitoring the amplitude of a differential analog signal (IN+, IN-) is composed of a differential Track&Hold stage (T&H) controlled by a first differential logic timing signal (TClk+, TClk-), tracking the differential analog input signal (IN+, IN-) during a tracking phase that corresponds to a high logic stage of the first differential timing signal (TClk+, TClk-), producing a differential output signal that is a replica of the input signal and storing it during a successive storing phase that corresponds to a low logic state of the first differential timing signal (TClk+, TClk-); a first differential output amplifier ( ) having inputs coupled to the output of the Track&Hold stage (T&H); a differential bistable circuit (LATCH-ECL), controlled by a second differential logic timing signal (DClk+, DClk-), having inputs coupled to the differential outputs of the first amplifier ( ) and producing a third differential logic control signal (S+, S-); a second multiplexed amplifier (Analog-Amp ), controlled by the third differential control signal (S+, S-), having inputs coupled to the output of the Track&Hold stage (T&H) and outputting a differential analog signal (OUT+, OUT-) of amplitude function of the amplitude of the differential input signal (IN+, IN-); a timing circuit (T C ) receiving at an input a differential logic synchronism signal (Clk+, Clk-) and generating the first differential timing signal (TClk+, TClk-) of said Track&Hold stage (T&H) and the second differential timing signal (DClk+, DClk-) of said bistable circuit (LATCH-ECL).

Abstract translation: 用于监视差分模拟信号（IN +，IN-）的幅度的全波整流器由由第一差分逻辑定时信号（TClk +，TClk-）控制的差分跟踪保持级（T＆H）组成，跟踪差分模拟输入 在对应于第一差分定时信号（TClk +，TClk-）的高逻辑级的跟踪阶段的信号（IN +，IN-）），产生作为输入信号的复制品的差分输出信号并在连续的期间存储 存储相位对应于第一差分定时信号（TClk +，TClk-）的低逻辑状态; 具有耦合到轨道和保持级（T＆amp; H）的输出的输入的第一差分输出放大器（@）; 由第二差分逻辑定时信号（DClk +，DClk-）控制的差分双稳态电路（LATCH-ECL）具有耦合到第一放大器（@）的差分输出的输入，并产生第三差分逻辑控制信号（S + S-）; 由第三差分控制信号（S +，S-）控制的第二多路复用放大器（Analog-Amp @），具有耦合到跟踪和保持级（T＆amp; H）的输出并输出差分模拟信号（OUT +，OUT-） 幅度函数的差分输入信号（IN +，IN-）的幅度; 定时电路（T @ C @）在输入端接收差分逻辑同步信号（Clk +，Clk-）并产生所述跟踪和保持级（T＆amp; H）的第一差分定时信号（TClk +，Tclk-）和第二差分定时信号 （LATCH-ECL）的（DClk +，DClk-）。