公开(公告)号：EP0778593B1

公开(公告)日：2000-11-22

申请号：EP95830506.2

申请日：1995-12-07

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  STMicroelectronics S.r.l.

Inventor： Capocelli, Piero ,  Zambrano, Raffaele ,  Pio, Federico ,  Riva, Carlo

IPC: H01F17/00 ,  H01L27/04

CPC classification number: H01F41/046 ,  H01F17/0033 ,  H01F2017/0086 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1049156A1

公开(公告)日：2000-11-02

申请号：EP99830262.4

申请日：1999-04-30

Applicant: STMicroelectronics S.r.l.

Inventor： Zambrano, Raffaele

IPC: H01L21/762 ,  H01L21/20

CPC classification number: H01L21/76264 ,  H01L21/76248 ,  H01L21/76278

Abstract: A process for manufacturing circuit structures (20,200) of the SOI type integrated on a semiconductor substrate (1,101) having a first type of conductivity, which process comprises the following steps:

forming at least one well (2) with a second type of conductivity in said semiconductor substrate (1);
forming a hole (4) in said at least one well (2);
coating the hole (4) with an insulating coating layer (5);
forming an opening (6) through the insulating coating layer (5) at the bottom of the hole (4);
filling the hole with an epitaxial layer (7) grown from a seed made accessible through said opening (6).

Abstract translation: 一种用于制造集成在具有第一类导电性的半导体衬底（1,101）上的SOI型电路结构（20,200）的方法，该方法包括以下步骤：在至少一个具有第二导电类型的阱（2）中形成 所述半导体衬底（1）; 在所述至少一个井（2）中形成孔（4）; 用绝缘涂层（5）涂覆孔（4）; 在孔（4）的底部通过绝缘涂层（5）形成开口（6）; 用从通过所述开口（6）可接近的种子生长的外延层（7）填充所述孔。

公开(公告)号：EP0996159A1

公开(公告)日：2000-04-26

申请号：EP98830597.5

申请日：1998-10-12

Applicant: STMicroelectronics S.r.l.

Inventor： Zambrano, Raffaele

IPC: H01L27/115 ,  H01L21/8247 ,  H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/11502 ,  H01L27/1085

Abstract: A circuit structure (1;110) integrated on a semiconductor substrate (2;20) and comprising:

at least one MOS device (4;40); and
at least one capacitor element (5;50);
said at least one MOS device (4;40) having conduction terminals (6,7;60,70) formed in the semiconductor layer and a control terminal (8;80) covered with an overlying insulating layer (12;120) of unreflowed oxide whereon said capacitor element is formed; and
said at least one capacitor element having a bottom electrode (9;90) and a top electrode (10;101).

Abstract translation: 集成在半导体衬底（2; 20）上的电路结构（1; 110），包括：至少一个MOS器件（4; 40）; 和至少一个电容器元件（5; 50）; 所述至少一个具有形成在所述半导体层中的导电端子（6,7; 60,70）的MOS器件（4; 40）和覆盖有未流过的上覆绝缘层（12; 120）的控制端子（8; 80） 形成所述电容器元件的氧化物; 并且所述至少一个电容器元件具有底部电极（9; 90）和顶部电极（10; 101）。