公开(公告)号：EP1324392A1

公开(公告)日：2003-07-02

申请号：EP01830821.3

申请日：2001-12-28

Applicant: STMicroelectronics S.r.l.

Inventor： Zambrano, Raffaele ,  Artoni, Cesare

IPC: H01L27/115 ,  H01L21/8246 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75 ,  H01L28/91

Abstract: A memory cell (30) of a stacked type is formed by a MOS transistor (32) and a ferroelectric capacitor (33). The MOS transistor (32) is formed in an active region (40) of a substrate (30) of semiconductor material and comprises a conductive region (34a). The ferroelectric capacitor (33) is formed on top of the active region and comprises a first and a second electrodes (45, 47) separated by a ferroelectric region (46). A contact region (44a) connects the conductive region (34a) of the MOS transistor to the first electrode (45) of the ferroelectric capacitor (33). The ferroelectric capacitor (33) has a non-planar structure, formed by a horizontal portion (45) and two side portions (48) extending transversely to, and in direct electrical contact with, the horizontal portion.

Abstract translation: 堆叠型存储单元（30）由MOS晶体管（32）和强电介质电容器（33）形成。 MOS晶体管（32）形成在半导体材料的衬底（30）的有源区（40）中并且包括导电区（34a）。 铁电电容器（33）形成在有源区的顶部，并且包括由铁电区（46）分开的第一和第二电极（45,47）。 接触区域（44a）将MOS晶体管的导电区域（34a）与铁电体电容器（33）的第一电极（45）连接。 铁电电容器（33）具有由水平部分（45）和与水平部分横向并直接电接触延伸的两个侧部（48）形成的非平面结构。

公开(公告)号：EP0996160A1

公开(公告)日：2000-04-26

申请号：EP98830598.3

申请日：1998-10-12

Applicant: STMicroelectronics S.r.l.

Inventor： Zambrano, Raffaele

IPC: H01L27/115 ,  H01L21/8247 ,  H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/11502 ,  H01L21/76801 ,  H01L21/76837 ,  H01L21/76877 ,  H01L27/0629 ,  H01L27/1085 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

Abstract: A contact structure for semiconductor devices which are integrated on a semiconductor layer and comprise:

at least one MOS device (3,30); and
at least one capacitor element (4,40); wherein
the contact (20;200) is provided at an opening (10,11;101,110) formed in an insulating layer (12;120) which overlies at least in part the semiconductor layer, the opening having its surface edges, walls and bottom coated with a metal layer (18;180) and filled with an insulating layer (19;190).

Abstract translation: 一种集成在半导体层上的半导体器件的接触结构，包括：至少一个MOS器件（3,30）; 和至少一个电容器元件（4,40）; 其中所述接触件（20; 200）设置在形成在绝缘层（12; 120）中的开口（10,11; 101,110）上，所述绝缘层至少部分地覆盖所述半导体层，所述开口具有其表面边缘，壁和底部 涂覆有金属层（18; 180）并填充有绝缘层（19; 190）。

公开(公告)号：EP0917185A1

公开(公告)日：1999-05-19

申请号：EP97830603.3

申请日：1997-11-14

Applicant: STMicroelectronics S.r.l.

Inventor： Zambrano, Raffaele

IPC: H01L21/3205 ,  H01L21/28

CPC classification number: H01L21/28273 ,  H01L21/28061 ,  H01L21/28525

Abstract: An in-situ deposition and doping process of one or more layers of polycrystalline silicon, for electronic semiconductor devices. The invention comprises at least a first growth step of a first intermediate layer (L1) of in-situ doped polycrystalline silicon and a second growth step of a second additional layer (L2) of polycrystalline silicon with a lower doping level compared to the first intermediate layer (L1) of polycrystalline silicon.

Abstract translation: 用于电子半导体器件的一层或多层多晶硅的原位沉积和掺杂工艺。 本发明包括至少第一生长步骤的原位掺杂多晶硅的第一中间层（L1）和与第一中间体相比具有较低掺杂水平的多晶硅的第二附加层（L2）的第二生长步骤 多晶硅层（L1）。

公开(公告)号：EP0917185B1

公开(公告)日：2009-01-07

申请号：EP97830603.3

申请日：1997-11-14

Applicant: STMicroelectronics S.r.l.

Inventor： Zambrano, Raffaele

IPC: H01L21/3205 ,  H01L21/28

CPC classification number: H01L21/28273 ,  H01L21/28061 ,  H01L21/28525

公开(公告)号：EP0703620B1

公开(公告)日：2001-01-10

申请号：EP94830444.9

申请日：1994-09-21

Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe

Inventor： Palara, Sergio ,  Zambrano, Raffaele

IPC: H01L27/02

CPC classification number: H01L27/0248

公开(公告)号：EP1324392B1

公开(公告)日：2009-12-09

申请号：EP01830821.3

申请日：2001-12-28

Applicant: STMicroelectronics S.r.l.

Inventor： Zambrano, Raffaele ,  Artoni, Cesare

IPC: H01L27/115 ,  H01L21/8246 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75 ,  H01L28/91

公开(公告)号：EP1207558A1

公开(公告)日：2002-05-22

申请号：EP00830762.1

申请日：2000-11-17

Applicant: STMicroelectronics S.r.l.

Inventor： Zambrano, Raffaele

IPC: H01L27/115 ,  H01L21/8246

CPC classification number: H01L27/11502 ,  H01L27/11507

Abstract: The invention relates to a contact structure for a ferroelectric memory device integrated in a semiconductor substrate (5) and comprising an appropriate control circuitry and a matrix array (15) of ferroelectric memory cells, wherein each cell includes a MOS device (3) connected to a ferroelectric capacitor (4);

the MOS device (3) having first and second conduction terminals (6A,6B) and being covered with an insulating layer (9); and
the ferroelectric capacitor (4) having a lower plate (11) formed on the insulating layer (9) above the first conduction terminals (6A) and connected electrically to the latter, which lower plate is covered with a layer of a ferroelectric material (12) and coupled capacitively to an upper plate (13).

Advantageously according to the invention, the contact structure comprises at least a plurality of plugs (10) filled with a non-conductive material between the first conduction terminals (6A) and the ferroelectric capacitor (4), and comprises a plurality of plugs (16) filled with a conductive material for the second conduction terminals (6B) or the control circuitry.

Abstract translation: 本发明涉及一种集成在半导体衬底（5）中的铁电存储器件的接触结构，包括一个合适的控制电路和铁电存储器单元的矩阵阵列（15），其中每个单元包括MOS器件（3），连接到 铁电电容器（4）; 所述MOS器件（3）具有第一和第二导电端子（6A，6B）并被绝缘层（9）覆盖; 和具有在第一导电端子（6A）上方形成在绝缘层（9）上并与之相连接的下板（11）的铁电电容器（4），并且与下一板电连接，该下板被铁电材料层 12）并且电容耦合到上板（13）。 有利地，根据本发明，接触结构包括在第一导电端子（6A）和铁电电容器（4）之间填充有非导电材料的至少多个插塞（10），并且包括多个插头（16） ）填充有用于第二导电端子（6B）或控制电路的导电材料。

公开(公告)号：EP0817274B1

公开(公告)日：2004-02-11

申请号：EP96830384.2

申请日：1996-07-05

Applicant: STMicroelectronics S.r.l.

Inventor： Magri', Angelo ,  Zambrano, Raffaele ,  Frisina, Ferruccio

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0611 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66712

Abstract: A MOS technology power device comprises a semiconductor substrate (1), a semiconductor layer (2) of a first conductivity type superimposed over the semiconductor substrate (1), an insulated gate layer (5,6,7;51,52,6,7) covering the semiconductor layer (2), a plurality of substantially rectilinear elongated openings (10) parallel to each other in the insulated gate layer, a respective plurality of elongated body stripes (3) of a second conductivity type formed in the semiconductor layer (2) under the elongated openings (10), source regions (4) of the first conductivity type included in the body stripes (3) and a metal layer (9) covering the insulated gate layer and contacting the body stripes and the source regions through the elongated openings. Each body stripe comprises first portions (31) substantially aligned with a first edge of the respective elongated opening and extending under a second edge of the elongated opening to form a channel region, each first portion (31) including a source region (4) extending substantially from a longitudinal axis of symmetry of the respective elongated opening to the second edge of the elongated opening, and second portions (32), longitudinally intercalated with the first portions (31), substantially aligned with the second edge of the elongated opening and extending under the first edge of the elongated opening to form a channel region, each second portion including a source region extending substantially from the longitudinal axis of symmetry to the first edge of the elongated opening, the first portions (31) and second portions (32) of the body stripes (3) being respectively aligned in a direction transversal to the longitudinal axis.

公开(公告)号：EP1049156B1

公开(公告)日：2009-02-18

申请号：EP99830262.4

申请日：1999-04-30

Applicant: STMicroelectronics S.r.l.

Inventor： Zambrano, Raffaele

IPC: H01L21/762 ,  H01L21/20

CPC classification number: H01L21/76264 ,  H01L21/76248 ,  H01L21/76278

公开(公告)号：EP1067605A1

公开(公告)日：2001-01-10

申请号：EP99830431.5

申请日：1999-07-05

Applicant: STMicroelectronics S.r.l.

Inventor： Casagrande, Giulio ,  Zambrano, Raffaele

IPC: H01L27/115 ,  H01L21/8242

CPC classification number: H01L27/11502 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/11507

Abstract: A memory cell (2) integrated in a semiconductor substrate (3) and comprised of a MOS device (4) connected in series to a capacitive element (5), wherein

the MOS device (4) has first and second conduction terminals (6),
the capacitive element (5) has a lower electrode (16) covered with a layer (17) of a dielectric material and coupled capacitively to an upper electrode (18),
said MOS device (4) is overlaid by at least one metallization layer (10,13), which metallization layer (10,13) is covered with at least one top insulating layer (11,14), that the capacitive element (5) is formed on the top insulating layer (11,14), and that said metallization layer (10,13) extends only between said MOS device (4) and said capacitive element (5).

Abstract translation: 一种集成在半导体衬底（3）中并由与电容元件（5）串联连接的MOS器件（4）组成的存储单元（2），其中MOS器件（4）具有第一和第二导电端子（6） ，所述电容元件（5）具有被电介质材料的层（17）覆盖并且电容地耦合到上电极（18）的下电极（16），所述MOS器件（4）被至少一个金属化层 （10,13），所述金属化层（10,13）被至少一个顶部绝缘层（11,14）覆盖，所述电容元件（5）形成在顶部绝缘层（11,14）上，以及 所述金属化层（10,13）仅在所述MOS器件（4）和所述电容元件（5）之间延伸。