公开(公告)号：EP1403927A1

公开(公告)日：2004-03-31

申请号：EP02425592.9

申请日：2002-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Zuliani, Paola ,  Giarda, Katia ,  Annunziata, Roberto

IPC: H01L27/105 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L29/66575

Abstract: A process for fabricating high-voltage drain-extension transistors, whereby the transistors are integrated in a semiconductor substrate (10) along with non-volatile memory cells comprising floating gate transistors, the process comprising at least the following steps:

defining respective active areas (1,2) for HV transistors and floating gate transistors in a common semiconductor substrate (10), with the active areas being separated from each other by insulating regions (3);
depositing a layer (4) of gate oxide onto the active areas;
depositing a layer (5) of polysilicon onto the gate oxide layer (4);
first masking and then etching through the polysilicon layer (5) to form gate regions (7) of the HV transistors;
performing a first dopant implantation to form first portions (9) of the high-voltage transistor junctions;
conformably depositing a dielectric layer (11) onto the whole substrate (10) to provide an interpoly layer of the floating gate transistor;
making openings (12) at the locations of the first portions (9) of the high-voltage transistor junctions;
performing, through the openings (12), a second dopant implantation to form second portions ( 13) of the high-voltage transistor junctions, with the perimetral areas of the gate regions and the active area of the floating gate transistor being screened off by the dielectric layer (11).

Abstract translation: 制造高压漏极延伸晶体管：（a）通过在高压晶体管结的第一部分的位置处形成开口; 和（b）通过开口进行第二掺杂剂注入，以形成高电压晶体管结的第二部分，栅极区域的周边区域和由电介质层屏蔽的浮动栅晶体管的有源区。 与包括浮栅晶体管的非易失性单元一起集成在半导体（10）衬底中的高电压漏极延伸晶体管的制造包括：（a）在公共半导体衬底中定义用于高电压晶体管和浮置栅极晶体管的各自的有效面积 其中所述有源区域通过绝缘区域（3）彼此分离; （b）在有源区上沉积栅极氧化物层（4）; （c）在栅极氧化物层上沉积多晶硅层; （d）通过多晶硅层进行膜掩蔽和蚀刻以形成晶体管的栅极区域（7）; （e）执行第一掺杂剂注入以形成晶体管结的第一部分（9）; （f）顺应地沉积介电层（11）以提供所述浮栅晶体管的多晶硅层; 和（g）通过开口（12）进行第二掺杂剂注入，以形成高电压晶体管结的第二部分（13），栅极区域的周边区域和浮置栅极晶体管的有源区域被电介质层屏蔽 。 在高压晶体管结的第一部分的位置处形成开口。

公开(公告)号：EP1020907A1

公开(公告)日：2000-07-19

申请号：EP99830007.3

申请日：1999-01-15

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico ,  Zuliani, Paola ,  Fratin, Lorenzo

IPC: H01L23/00 ,  H01L23/58

CPC classification number: H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Chip Outline Band (COB) structure for an integrated circuit integrated in a semiconductor chip having a semiconductor substrate (1) of a first conductivity type and biased at a common reference potential (GND) of the integrated circuit, the COB structure comprising a substantially annular region (3;30) formed in the substrate (1) along a periphery thereof, and at least one annular conductor region (40,60) superimposed on and contacting the substantially annular region (3;30), characterized in that said substantially annular region (3;30) is electrically connected at said common reference potential (GND).

Abstract translation: 用于集成在具有第一导电类型的半导体衬底（1）并且被集成电路的公共参考电位（GND）偏置的半导体芯片中的集成电路的芯片轮廓带（COB）结构，所述COB结构包括大致环形 沿着其周边形成在所述基板（1）中的区域（3; 30）以及叠置在所述基本环形区域（3; 30）上并且接触所述大致环形区域（3; 30）的至少一个环形导体区域（40,60），其特征在于， 区域（3; 30）在所述公共参考电位（GND）处电连接。