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    A method of producing MOSFET transistors by means of tilted implants
    5.
    发明授权
    A method of producing MOSFET transistors by means of tilted implants 失效
    一种用于通过倾斜注入的手段制备MOSFET晶体管的方法

    公开(公告)号：EP0874389B1

    公开(公告)日：2007-08-01

    申请号：EP97830182.8

    申请日：1997-04-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fratin, Lorenzo ,  Riva, Carlo

    IPC: H01L21/265 ,  H01L21/28 ,  H01L29/423

    CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L21/28123 ,  H01L29/4238

    Abstract: The method described provides for the following steps: delimiting active areas (81) on a substrate, forming gate electrodes (82, 83, 88) insulated from the substrate on the active areas, and subjecting the front surface of the substrate to several implantation steps with doping ion beams to form source and drain regions with the use of the gate electrodes as masks. The direction of the implantation beam is defined by an angle of inclination to the front surface and by an orientation (45 DEG , 135 DEG , 225 DEG , 315 DEG ) to a reference line (80) on the front surface. To avoid performing numerous implantation steps without foregoing channels of uniform and constant length (L''), the widths of the gate electrode strips (82, 83, 88) are determined at the design stage in dependence on the orientation of the strips to the reference line (80) and on the orientation of the directions of the implant beams.

    Periphery barrier structure for integrated circuits
    6.
    发明公开
    Periphery barrier structure for integrated circuits 有权
    BarrierenstrukturfürPeripherie Integrierter Schaltkreise

    公开(公告)号：EP1020907A1

    公开(公告)日：2000-07-19

    申请号：EP99830007.3

    申请日：1999-01-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pio, Federico ,  Zuliani, Paola ,  Fratin, Lorenzo

    IPC: H01L23/00 ,  H01L23/58

    CPC classification number: H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Chip Outline Band (COB) structure for an integrated circuit integrated in a semiconductor chip having a semiconductor substrate (1) of a first conductivity type and biased at a common reference potential (GND) of the integrated circuit, the COB structure comprising a substantially annular region (3;30) formed in the substrate (1) along a periphery thereof, and at least one annular conductor region (40,60) superimposed on and contacting the substantially annular region (3;30), characterized in that said substantially annular region (3;30) is electrically connected at said common reference potential (GND).

    Abstract translation: 用于集成在具有第一导电类型的半导体衬底（1）并且被集成电路的公共参考电位（GND）偏置的半导体芯片中的集成电路的芯片轮廓带（COB）结构，所述COB结构包括大致环形 沿着其周边形成在所述基板（1）中的区域（3; 30）以及叠置在所述基本环形区域（3; 30）上并且接触所述大致环形区域（3; 30）的至少一个环形导体区域（40,60），其特征在于， 区域（3; 30）在所述公共参考电位（GND）处电连接。

    A method of producing MOSFET transistors by means of tilted implants
    7.
    发明公开
    A method of producing MOSFET transistors by means of tilted implants 失效
    Ein Verfahren zur Herstellung von MOSFET-Transistoren mittels geneigten Implantierungen

    公开(公告)号：EP0874389A1

    公开(公告)日：1998-10-28

    申请号：EP97830182.8

    申请日：1997-04-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fratin, Lorenzo ,  Riva, Carlo

    IPC: H01L21/265 ,  H01L21/28 ,  H01L29/423

    CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L21/28123 ,  H01L29/4238

    Abstract: The method described provides for the following steps: delimiting active areas (81) on a substrate, forming gate electrodes (82, 83, 88) insulated from the substrate on the active areas, and subjecting the front surface of the substrate to several implantation steps with doping ion beams to form source and drain regions with the use of the gate electrodes as masks. The direction of the implantation beam is defined by an angle of inclination to the front surface and by an orientation (45°, 135°, 225°, 315°) to a reference line (80) on the front surface. To avoid performing numerous implantation steps without foregoing channels of uniform and constant length (L''), the widths of the gate electrode strips (82, 83, 88) are determined at the design stage in dependence on the orientation of the strips to the reference line (80) and on the orientation of the directions of the implant beams.

    Abstract translation: 所描述的方法提供了以下步骤：限定衬底上的有源区域（81），形成与有源区域上的衬底绝缘的栅电极（82,83,88），并对衬底的前表面进行若干注入步骤 使用掺杂离子束形成源区和漏区，使用栅电极作为掩模。 注入光束的方向由前表面的倾斜角以及正面（45°，135°，225°，315°）到前表面上的参考线（80）的方向限定。 为了避免执行大量的注入步骤而没有前后通道的均匀和恒定的长度（L“），栅极电极条（82,83,88）的宽度根据条带的取向在设计阶段确定 参考线（80）和植入物束的方向的取向。

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