公开(公告)号：EP1750278A1

公开(公告)日：2007-02-07

申请号：EP06115106.4

申请日：2006-06-07

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Micheloni, Rino

IPC: G11C11/56

CPC classification number: G11C16/10 ,  G11C11/5628

Abstract: When the threshold voltage of a cell of a four-level FLASH memory device, that includes an array of singularly addressable preliminarily erased memory cells each capable of storing a two-bit datum, is verified to have reached the desired distribution, the cell is read using a test read voltage smaller than or equal to the program voltage. In this situation the voltage V S on the source node is surely negligible and the programmed state of the cell may be correctly verified.
A novel architecture of a page buffer is also provided.

Abstract translation: 当一台四电平快闪存储器装置的单元的阈值电压，没有包括在单独可寻址的预先擦除的存储器单元每个都能够存储一个两比特的日期的阵列，被验证为已达到期望的分布，该单元被读 使用测试读取电压小于或等于所述编程电压。 在这种情况下在源节点上的电压V S是可靠地忽略不计，单元的编程状态可被正确验证。 因此，提供的页缓冲器的一种新颖的体系结构。

公开(公告)号：EP1748446A1

公开(公告)日：2007-01-31

申请号：EP05106975.5

申请日：2005-07-28

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Micheloni, Rino ,  Crippa, Luca ,  Ravasio, Roberto

IPC: G11C11/56

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3436 ,  G11C2211/5621 ,  G11C2211/5642

Abstract: A method for programming an electrically programmable memory (100) is provided. The electrically programmable memory includes a plurality of memory cells (110) arranged in individually-selectable memory cell sets each including at least one memory cell, a plurality of distinct memory cell programming states (201, 202, 203, 204) corresponding to a number N >=2 of data bits storable in each memory cell. The data bits include at least a first data bits group (LSB) and a second data bits group (MSB); the first data bits groups and, respectively, the second data bits groups stored in the memory cells of one of said individually-selectable memory cell sets form at least a first memory page and a second memory page, respectively, the first and second memory pages being individually addressable.
The programming method comprises:
- causing the memory cells of a selected memory cells set to be brought into a predetermined, starting programming state (201);
- receiving a target value for the first data bits groups of the memory cells of the selected memory cells set;
- receiving a target value for the second data bits groups of the memory cells of the selected memory cells set;
- after having received the target values of both the first and the second data bits groups, applying to the memory cells of the selected memory cells set a programming sequence (350) adapted to cause the memory cells of the selected memory cells sets to be brought into a target programming state (201,202,203,204) jointly determined by the target values of the first and second data bits groups.

Abstract translation: 提供了一种用于编程电可编程存储器（100）的方法。 电可编程存储器包括布置在可单独选择的存储单元组中的多个存储单元（110），每个存储单元组包括至少一个存储单元，多个不同的存储单元编程状态（201,202,203,204） N> = 2可存储在每个存储单元中的数据位。 数据位包括至少第一数据位组（LSB）和第二数据位组（MSB）; 第一数据位组和分别存储在所述可单独选择的存储单元组之一的存储单元中的第二数据位组分别形成至少第一存储器页和第二存储器页，第一和第二存储器页 单独寻址。 编程方法包括： - 使所设置的选定存储单元的存储单元进入预定的开始编程状态（201）; - 接收所选存储单元组的存储单元的第一数据位组的目标值; - 接收所选存储单元组的存储单元的第二数据位组的目标值; - 在已经接收到第一和第二数据位组之间的目标值之后，向所选择的存储单元的存储单元施加设置适于使所选择的存储单元组的存储单元被带入的编程序列（350） 转换为由第一和第二数据位组的目标值共同确定的目标编程状态（201,202,203,204）。

公开(公告)号：EP1748443A1

公开(公告)日：2007-01-31

申请号：EP05106973.0

申请日：2005-07-28

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Micheloni, Rino

IPC: G11C5/02 ,  G11C11/56

CPC classification number: G11C11/5628 ,  G11C5/025 ,  G11C11/5642 ,  G11C2211/5642

Abstract: A memory device (100) is provided. The memory device includes a matrix (105) of memory cells (110) adapted to store data and arranged in a plurality of bit lines (BLe, BLo), the bit lines extending along a first direction (Y); a page buffer (130) adapted to interface the matrix with a downstream circuitry (125c, 140), the page buffer comprising a plurality of read/program units (205(i)). Each read/program unit is associated with and operatively couplable to at least one bit line. The memory device further includes at least two groups each including at least two respective read/program units, wherein the read/program units of a generic one of said groups are generically aligned along the first direction. The at least two groups are generically aligned along a second direction (X) transversal to the first direction. The memory device further includes at least one signal track (BITOUT) associated with each one of said groups for conveying signals corresponding to data read from the memory cells to the downstream circuitry are provided. Said at least one signal track is shared by the at least two read/program units of the corresponding group. The memory device further includes means (410) for selectively assigning the at least one signal track to one of the associated read/program unit at a time among the at least two read/program units of the group associated with said signal track.

Abstract translation: 提供存储器件（100）。 存储器件包括适于存储数据并且布置在沿着第一方向（Y）延伸的位线的多个位线（BLe，BLo））中的存储器单元（110）的矩阵（105）。 适于将矩阵与下游电路（125c，140）接口的页缓冲器（130），所述页缓冲器包括多个读/程序单元（205（i））。 每个读取/编程单元与至少一个位线相关联并可操作地耦合到至少一个位线。 存储器件还包括至少两组，每组包括至少两个相应的读/写单元，其中所述组中的通用一个的读/程单元沿第一方向一般对准。 所述至少两个组沿着沿着所述第一方向横向的第二方向（X）被一般排列。 存储器装置还包括与所述组中的每一个相关联的至少一个信号轨道（BITOUT），用于将对应于从存储器单元读取的数据传送到下游电路的信号。 所述至少一个信号轨道由对应组的至少两个读/写单元共享。 存储器件还包括用于在与所述信号轨道相关联的组的至少两个读取/编程单元中的一个时间将至少一个信号轨迹选择性地分配给相关联的读取/编程单元中的一个的装置（410）。

公开(公告)号：EP1746605A1

公开(公告)日：2007-01-24

申请号：EP05106782.5

申请日：2005-07-22

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Missiroli, Chiara ,  Micheloni, Rino

IPC: G11C16/26 ,  G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/26

Abstract: A reading method of a NAND memory device including the steps of: first connecting a first end terminal (12a) of a stack (12) of cells (3, 3', 3") to a reference line (13); second connecting a second end terminal (12b) of the stack (12) of cells (3, 3', 3") to a respective bitline (10); charging the bitline (10) to a predetermined bitline read voltage (V DR ), wherein one of the steps of first connecting and second connecting is carried out before charging the bitline (10) and the other of the steps of first connecting and second connecting is carried out after charging the bitline (10). An order of carrying out the steps of first connecting and second connecting is determined based on an address (MSB; AL2) of a selected cell (3', 3") .

Abstract translation: 一种NAND存储装置的读取方法，包括以下步骤：首先将单元（3,3'，3“）的堆叠（12）的第一端子（12a）连接到参考线（13）;第二连接 单元（3,3'，3“）的堆叠（12）的第二端子（12b）到相应的位线（10）; 将位线（10）充电到预定的位线读取电压（V DR），其中在对位线（10）充电之前执行第一连接和第二连接的步骤之一，并且第一连接和第二连接的另一个步骤 在对位线（10）充电之后进行。 基于选择的单元（3'，3“）的地址（MSB; AL2）确定执行第一连接和第二连接步骤的顺序。

公开(公告)号：EP1909290B1

公开(公告)日：2009-10-07

申请号：EP06119452.8

申请日：2006-08-24

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Micheloni, Rino ,  Crippa, Luca ,  Ravasio, Roberto ,  Pio, Federico

IPC: G11C16/34

CPC classification number: G11C16/344

公开(公告)号：EP1909290A1

公开(公告)日：2008-04-09

申请号：EP06119452.8

申请日：2006-08-24

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Micheloni, Rino ,  Crippa, Luca ,  Ravasio, Roberto ,  Pio, Federico

IPC: G11C16/34

CPC classification number: G11C16/344

Abstract: A method for operating a flash memory device ( 100 ) is proposed. The memory device includes a matrix of memory cells ( 110 ) each one having a programmable threshold voltage (V T ) defining a value stored in the memory cell. The method includes the steps of crasing a block ( 115 ) of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell (110 0e ) of the block for writing a target value; restoring the threshold voltage of a subset (110 0e ; 110 1o ) of the memory cells of the block to the compacting range, the subset consisting of the at least one first memory cell (110 0e ) and/or at least one second memory cell of the block (110 1o ) being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

Abstract translation: 一种用于操作闪存器件（100）的方法，提出了 所述存储器装置包含存储单元的矩阵（110）每一个具有 - 定义存储在存储单元中的值的可编程阈值电压（V T）。 该方法包括crasing存储器单元的块（115），以及预定义的压实范围内压实块的存储器单元的阈值电压，worin压实的步骤的步骤包括：选择至少一个第一存储单元（110 0E）用于写入目标值的块的; 的子集的阈值电压（110 0E; 110 1O）恢复该块的存储器单元内的压实范围，所述子集由......组成所述至少一个第一存储单元（110奥斯特）和/或至少一个第二存储单元 块（110 1O）邻近所述至少一个第一存储单元的; 并至少部分地写入目标值到所述至少一个第一存储单元。

公开(公告)号：EP1901309A1

公开(公告)日：2008-03-19

申请号：EP06425631.6

申请日：2006-09-13

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/32 ,  G11C29/00

CPC classification number: G11C29/02 ,  G11C16/04 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/1204

Abstract: The evaluation time (Teval) of the programmed or erased state of a cell of the NAND memory array is set for the individual memory device in a way that at least partially compensates the generally large spread of parasitic capacitance values of the array bitlines in the mass production fabrication process of these devices.

Abstract translation: NAND存储器阵列的单元的编程或擦除状态的评估时间（Teval）以单个存储器件的方式被设置，该方式至少部分补偿了质量中阵列位线的寄生电容值的普遍大的扩展 这些设备的生产制造过程。

公开(公告)号：EP1883076A1

公开(公告)日：2008-01-30

申请号：EP06425536.7

申请日：2006-07-28

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: G11C16/10 ,  G11C11/56

CPC classification number: G11C16/10 ,  G11C7/18 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427

Abstract: The capacitive coupling between two adjacent bitlines of a NAND memory device is relevant and this may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them.
According to the disclosed method, first the even (odd) bitlines that include cells not to be programmed (BLE ,...,BLE ) are biased with a first voltage for inhibiting them from being programmed, typically the supply voltage (VDD), while the even (odd) bitlines that include cells to be programmed are grounded. Successively, the adjacent odd (even) bitlines (BLO ,...,BLO ) are biased at the supply voltage (VDD) or at an auxiliary voltage, for boosting the bias voltage of the even (odd) bitlines above the supply voltage.
With this expedient, the bias voltage of the even (odd) bitlines that include cells not to be programmed is boosted because of the relevant parasitic coupling capacitances between adjacent bitlines. Therefore, no dedicated charge pump generator is needed.

Abstract translation: NAND存储器件的两个相邻位线之间的电容耦合是相关的，并且这可以用于提升不被编程的位线的电压，以便阻止对它们的编程操作。 根据所公开的方法，首先，包含不被编程的单元（BLE <1>，...，BLE ）的偶数（奇数）位线被用于阻止它们被编程的第一电压偏置，通常 电源电压（VDD），而包括要编程的单元的偶数（奇数）位线接地。 接着，相邻的奇数（偶数）位线（BLO <0>，...，BLO ）偏置在电源电压（VDD）或辅助电压，用于升压偶数（奇数） 位于电源电压以上。 通过这种方式，由于相邻位线之间的相关寄生耦合电容，包括不编程单元的偶数（奇数）位线的偏置电压会升高。 因此，不需要专用的电荷泵发电机。

公开(公告)号：EP1870901A1

公开(公告)日：2007-12-26

申请号：EP06115809.3

申请日：2006-06-21

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Micheloni, Rino

IPC: G11C11/56 ,  G11C7/10 ,  G11C16/24

CPC classification number: G11C7/1021 ,  G11C7/1039 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A page buffer (130) comprised in an electrically programmable memory device (100) is provided. The memory device includes also a plurality of memory cells (110), a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell, and at least one read/program unit (205) having a coupling line (SO) operatively associable with selected memory cells. The read/program unit is adapted to at least temporarily store data bits read from or to be written into selected memory cells and comprises programming state change enabling means (230-1,230-2,252,254,256,258,272,274,276,278) for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential. The programming state change enabling means comprises reading means (256,258,260,230-2), receiving means (252,254,230-1), and combining means (272,274) activatable during a combining phase. The combining means includes a coupling electrical path between the reading means and the receiving means, said coupling electrical line being kept isolated from the coupling electrical path during said combining phase.

Abstract translation: 提供包括在电可编程存储器件（100）中的页缓冲器（130）。 存储器件还包括多个存储器单元（110），对于每个存储器单元定义的多个不同的编程状态，对应于可存储在每个存储单元中的数据位数N> = 2，以及至少一个读/ 单元（205）具有与所选择的存储器单元可操作地相关联的耦合线（SO）。 读/写单元适于至少临时存储从或将被写入所选择的存储单元中的数据位，并且包括编程状态改变使能装置（230-1,230-2,252,254,256,258,272,274,276,278），用于选择性地启用所选存储器的编程状态的改变 通过使耦合线在程序使能电位和程序禁止电位之间采取一个单元。 编程状态改变使能装置包括读取装置（256,258,260,230-2），接收装置（252,254,230-1）以及在组合阶段可激活的组合装置（272,274）。 组合装置包括在读取装置和接收装置之间的耦合电路，所述耦合电线在所述组合阶段期间与耦合电路保持隔离。

公开(公告)号：EP1729302A1

公开(公告)日：2006-12-06

申请号：EP05104656.3

申请日：2005-05-31

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Ragone, Giancarlo ,  Sangalli, Miriam ,  Micheloni, Rino

IPC: G11C11/56 ,  G11C16/28 ,  G11C16/30

CPC classification number: G11C11/5642 ,  G11C7/04 ,  G11C16/30

Abstract: A circuit comprises at least one memory cell ( 110 ) adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator ( 300 ) is provided for generating a voltage (Vo) to be supplied to the at least one memory cell ( 110 ) for retrieving the data stored therein, the voltage generator including first means ( 305 ) adapted to cause the generated voltage take a value in a set of target values including at least one target value (Vr-1,Vr-2,Vr-3,Vfy-1,Vfy-2,Vfy-3), corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means ( Mt,Rs,325, R1,R2,330 ) for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element ( Mt ) having said electrical characteristic.

Abstract translation: 电路包括至少一个存储单元（110），其适于根据其电特性的值存储数据，其根据第一变化规律表现出与温度的变化性; 提供电压发生器（300），用于产生要提供给所述至少一个存储单元（110）的电压（Vo），用于检索存储在其中的数据，所述电压发生器包括第一装置（305），其适于使所产生的电压 在包含至少一个目标值（Vr-1，Vr-2，Vr-3，Vfy-1，Vfy-2，Vfy-3）的目标值集合中取值， 记忆单元 电压发生器包括用于使所产生的电压所采用的值根据规定的第二变化规律随温度变化的第二装置（Mt，Rs，325，R1，R2,330），该规定的第二变化规律利用具有所述电特性的补偿电路元件 。