公开(公告)号：EP1696490A1

公开(公告)日：2006-08-30

申请号：EP05425102.0

申请日：2005-02-25

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio

IPC: H01L29/78

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095

Abstract: Compensation power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity comprising a plurality of elemental units, each elemental unit comprising:

a body region (40) of a second type of conductivity realised on a semiconductor layer (20) of the first type of conductivity formed on the semiconductor substrate (100),
a column region (50) of the second type of conductivity realised in said semiconductor layer (20) below the body region (40),

wherein the semiconductor layer (20) comprises a plurality of semiconductor layers (21,22,23,24), overlapped on each other, wherein the resistivity of each layer is different from that of the other layers and in that said column region (50) comprises a plurality of doped sub-regions (51,52,53,54), each realised in one of said semiconductor layers (21,22,23,24), wherein the dopant concentration of each doped sub-region (51,52,53,54) is such as to realise a balance between the total amount of charge of a first conductivity type and of a second conductivity type in each couple of layers and subregions.

Abstract translation: 集成在包括多个元件单元的第一导电类型的半导体衬底（100）上的补偿电力电子器件（30），每个元件单元包括：在半导体层上实现的第二导电类型的体区（40） 在所述半导体衬底（100）上形成的所述第一类型导电体的导体（20），在所述半导体层（20）中实现的所述第二导电类型的列区域（50），其中所述半导体层 （20）包括彼此重叠的多个半导体层（21,22,23,24），其中每个层的电阻率不同于其它层的电阻率，并且所述列区域（50）包括多个 的掺杂子区域（51,52,53,54），其分别在所述半导体层（21,22,23,24）中的一个中实现，其中每个掺杂子区域（51,52,53， 54）实现了af的总费用之间的平衡 第一导电类型和第二导电类型在每对层和子区域。