公开(公告)号：EP2299481A2

公开(公告)日：2011-03-23

申请号：EP10015719.7

申请日：2006-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio ,  Rascuna, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity whereon a drain semiconductor layer (20) is formed, characterised in that it comprises the following steps:
- forming at least a first semiconductor epitaxial layer (21) of the first type of conductivity of a first value of resistivity (ρ 1 ) forming the drain epitaxial layer (20) on the semiconductor substrate (100),
- forming in the first semiconductor layer (21) first sub-regions (51) of a second type of conductivity by means of a first selective implant step with a first implant dose (Φ 1P ),
- forming in the first semiconductor layer (21) second sub-regions (D1, D1a) of the first type of conductivity by means of a second implant step with a second implant dose (Φ 1N ),
- forming a surface semiconductor layer (23) wherein body regions (40) of the second type of conductivity are formed being aligned with the first sub-regions (51),
- carrying out a thermal diffusion process so that the first sub-regions (51) form a single electrically continuous column region (50) being aligned and in electric contact with the body regions (40).

Abstract translation: 用于制造集成在其上形成漏极半导体层（20）的第一导电类型的半导体衬底（100）上的多漏功率电子器件（30）的工艺，其特征在于其包括以下步骤： - 在 在所述半导体衬底（100）上形成漏极外延层（20）的第一电阻率值（ρ1）的第一导电类型的第一半导体外延层（21）， - 在所述第一半导体层（21） 借助于具有第一注入剂量（Φ1P）的第一选择性注入步骤的第二导电类型的第一子区域（51）;在第一半导体层（21）中形成第二导电类型的第二子区域（D1，D1a） 借助于具有第二注入剂量（Φ1N）的第二注入步骤的第一导电类型， - 形成表面半导体层（23），其中形成第二导电类型的本体区域（40）与第一子区域 - 区域（51）， - carryin 形成热扩散工艺，使得第一子区域（51）形成与主体区域（40）对准并电接触的单个电连续柱状区域（50）。

公开(公告)号：EP1742259A1

公开(公告)日：2007-01-10

申请号：EP05425494.1

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio ,  Rascuna, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity whereon a drain semiconductor layer (20) is formed, characterised in that it comprises the following steps:
- forming at least a first semiconductor epitaxial layer (21) of the first type of conductivity of a first value of resistivity (ρ 1 ) forming the drain epitaxial layer (20) on the semiconductor substrate (100),
- forming first sub-regions (51) of a second type of conductivity by means of a first selective implant step with a first implant dose (Φ 1P ),
- forming second sub-regions (D1,D1a) of the first type of conductivity by means of a second implant step with a second implant dose (Φ 1N ),
- forming a surface semiconductor layer (23) wherein body regions (40) of the second type of conductivity are formed being aligned with the first sub-regions (51),
- carrying out a thermal diffusion process so that the first sub-regions (51) form a single electrically continuous column region (50) being aligned and in electric contact with the body regions (40).

Abstract translation: 一种集成在形成漏极半导体层（20）的第一导电类型的半导体衬底（100）上的多漏极功率电子器件（30）的制造方法，其特征在于包括以下步骤： 至少形成在所述半导体衬底（100）上形成所述漏极外延层（20）的电阻率（α）的第一值的第一类型的导电性的第一半导体外延层（21）， - 形成所述第一子区域（51） 通过具有第一注入剂量（| 1P）的第一选择性注入步骤，通过第二种注入步骤形成第一类型导电性的第二子区域（D1，D1a） 第二植入剂量（| 1N）， - 形成表面半导体层（23），其中形成第二导电类型的体区（40）与第一子区（51）对准， - 执行热扩散过程 使得第一子区域（51）fo rm是单个电连续柱区域（50），其对准并与身体区域（40）电接触。

公开(公告)号：EP1742258A1

公开(公告)日：2007-01-10

申请号：EP05425493.3

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio ,  Rascuna, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity, comprising the following steps:
forming a first semiconductor layer (21) of the first type of conductivity and of a first resistivity (ρ 1 ) value on the semiconductor substrate (100),
forming at least a second semiconductor layer (22) of a second type of conductivity of a second resistivity (ρ 2 ) value on the first semiconductor layer (21),
forming, in this at least a second semiconductor layer (22), a first plurality of implanted regions (D1) of the first type of conductivity by means of a first selective implant step with a first implant dose (Φ 1 ) ,
forming, above this at least a second semiconductor layer (22), a superficial semiconductor layer (26) of the first type of conductivity of a third resistivity (ρ 6 ) value,
forming in the surface semiconductor layer (26) body regions (40) of the second type of conductivity, the body regions (40) being aligned with portions of the semiconductor layer (22) free from the plurality of implanted regions (D1),
carrying out a thermal diffusion step so that the plurality of implanted regions (D1) form a plurality of electrically continuous implanted column regions (D) along this at least a second semiconductor layer (22), the plurality of column implanted regions (D) delimiting a plurality of column regions (50) of the second type of conductivity aligned with the body regions (40).

Abstract translation: 用于制造集成在第一导电类型的半导体衬底（100）上的多漏功率电子器件（30）的工艺，包括以下步骤：形成第一导电类型的第一半导体层（21）和第一导电类型的第一半导体层 在所述半导体衬底（100）上的第一电阻率（ρ1）值，在所述第一半导体层（21）上形成至少第二电阻率（ρ2）值的第二导电类型的第二半导体层（22），从而形成 通过具有第一注入剂量（Φ1）的第一选择注入步骤在该至少第二半导体层（22）上形成具有第一导电类型的第一多个注入区域（D1），在该至少一个注入区域 第二半导体层（22）;第三电阻率（ρ6）值的第一导电类型的表面半导体层（26），其在表面半导体层（26）中形成第二导电类型的体区域（40） 身体部位（ 40）与没有所述多个注入区域（D1）的所述半导体层（22）的部分对准，执行热扩散步骤，使得所述多个注入区域（D1）形成多个电连续注入柱区域 D）沿所述至少第二半导体层（22）延伸，所述多个列注入区（D）限定与所述体区（40）对齐的所述第二导电类型的多个列区（50）。

公开(公告)号：EP1742249A1

公开(公告)日：2007-01-10

申请号：EP05425495.8

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Ferruccio ,  Saggio, Mario Giuseppe

IPC: H01L21/04 ,  H01L29/78 ,  H01L29/24 ,  H01L29/423

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068

Abstract: Method for manufacturing a vertical power MOS transistor on a semiconductor substrate (10) with wide band gap comprising a first superficial semiconductor layer (11) with wide band gap of a first type of conductivity, comprising the steps of:
- forming trench regions (13) in the first superficial semiconductor layer (11),
- filling in said trench regions (13) by means of a second semiconductor layer (14) with wide band gap of a second type of conductivity, so as to form semiconductor portions (15) of the second type of conductivity contained in the first superficial semiconductor layer (11),
- carrying out at least one ion implantation of a first type of dopant in the semiconductor portions (15) for forming respective implanted body regions (19) of said second type of conductivity,
- carrying out at least one ion implantation of a second type of dopant in each of the implanted body regions (19) for forming at least one implanted source region (23) of the first type of conductivity inside the implanted body regions (19),
- carrying out an activation thermal process of the first and second type of dopant with low thermal budget suitable to complete said formation of the implanted body and source regions (19,23).

Abstract translation: 1。一种用于在具有宽带隙的半导体衬底（10）上制造垂直功率MOS晶体管的方法，所述宽带隙包括具有第一导电类型的宽带隙的第一表面半导体层（11），所述方法包括以下步骤： - 形成沟槽区域 ）在第一表面半导体层（11）中， - 通过具有第二导电类型的宽带隙的第二半导体层（14）填充所述沟槽区域（13），从而形成半导体部分（15） 包含在所述第一表面半导体层（11）中的第二导电类型， - 在所述半导体部分（15）中执行至少一次第一类型掺杂物的离子注入，以形成所述第二表面 - 在每个注入体区（19）中进行至少一次第二类型掺杂剂的离子注入，以形成至少一个第一类型导电性绝缘体的注入源区（23） （19）， - 以低热预算执行第一和第二类型掺杂物的激活热处理，适于完成所述注入体区和源区（19,23）的所述形成。

公开(公告)号：EP1742271A1

公开(公告)日：2007-01-10

申请号：EP05425491.7

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Ferruccio ,  Saggio, Mario Giuseppe ,  Magri', Angelo

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/336 ,  H01L29/423

CPC classification number: H01L29/7802 ,  H01L21/046 ,  H01L21/047 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/6653 ,  H01L29/7835

Abstract: Method for manufacturing electronic devices on a semiconductor substrate (1,1a;10,11) with wide band gap comprising the steps of:
- forming a screening structure (3a,20) on said semiconductor substrate (1,1a;10,11) comprising at least a dielectric layer (2,20) which leaves a plurality of areas of said semiconductor substrate (1,1a;10,11) exposed,
- carrying out at least a ion implantation of a first type of dopant in said semiconductor substrate (1,1a;10,11) to form at least a first implanted region (4,40),
carrying out at least a ion implantation of a second type of dopant in said semiconductor substrate (1,1a;10,11) to form at least a second implanted region (6,6c;60,61) inside said at least a first implanted region (4,40),
- carrying out an activation thermal process of the first type and second type of dopant with low thermal budget suitable to complete said formation of said at least first and second implanted regions (4,40;6,60).

Abstract translation: 一种在具有宽带隙的半导体衬底（1,1a; 10,11）上制造电子器件的方法，包括以下步骤： - 在所述半导体衬底（1,1a; 10,11）上形成屏蔽结构（3a，20） 至少包括留下所述半导体衬底（1,1a; 10,11）的多个区域的电介质层（2,20），至少在所述半导体衬底中执行第一类型的掺杂剂的离子注入 （1,1a; 10,11）以形成至少第一注入区域（4,40），在所述半导体衬底（1,1a; 10,11）中至少执行第二类型掺杂剂的离子注入至 在所述至少第一注入区域（4,40）内形成至少第二注入区域（6,6c; 60,61）， - 以低热预算执行所述第一类型和第二类型掺杂剂的激活热处理 适于完成所述至少第一和第二注入区域（4,40; 6,60）的所述形成。

公开(公告)号：EP2290697A1

公开(公告)日：2011-03-02

申请号：EP10174803.6

申请日：2010-09-01

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Murabito, Domenico ,  Magrí, Angelo

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/336 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/0634 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7811

Abstract: A high voltage semiconductor device comprising a semiconductor substrate (2) covered by an epitaxial layer (3) of a first type of conductivity having a plurality of column structures (4) comprising high aspect ratio deep trenches, said epitaxial layer (3) being covered by an active surface area (5), each of the column structures (4) comprising an external portion (6) formed by a silicon epitaxial layer of a second type of conductivity, and having a dopant charge which counterbalances the dopant charge in said epitaxial layer (3) outside said column structures (4), a dielectric filling portion (7) filling up said deep trench, and said external portion (6) having a dopant concentration with a variable concentration profile having a maximum near an interface with said epitaxial layer (3).

Abstract translation: 一种高电压半导体器件，包括由第一导电类型的外延层（3）覆盖的半导体衬底（2），所述外延层具有包括高纵横比深沟槽的多个列结构（4），所述外延层（3）被覆盖 通过有源表面区域（5），每个列结构（4）包括由第二导电类型的硅外延层形成的外部部分（6），并且具有使所述外延层中的掺杂剂电荷平衡的掺杂剂电荷 在所述列结构（4）外部的层（3），填充所述深沟槽的介电填充部分（7），并且所述外部部分（6）具有可变浓度分布的掺杂浓度，所述掺杂浓度具有与所述外延 层（3）。

公开(公告)号：EP1873837A1

公开(公告)日：2008-01-02

申请号：EP06425448.5

申请日：2006-06-28

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Murabito, Domenico ,  Frisina, Ferruccio

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/78 ,  H01L21/329 ,  H01L21/336 ,  H01L29/417 ,  H01L29/08 ,  H01L21/20 ,  H01L21/324 ,  H01L29/739 ,  H01L29/872 ,  H01L29/732

CPC classification number: H01L29/7811 ,  H01L21/324 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872

Abstract: A process for manufacturing a semiconductor power device envisages the steps of: providing a body (3) made of semiconductor material having a first top surface (3a); forming an active region (4a; 29, 30) with a first type of conductivity in the proximity of the first top surface (3a) and inside an active portion (1a) of the body (3); and forming an edge-termination structure (4b, 5). The edge-termination structure is formed by: a ring region (5) having the first type of conductivity and a first doping level, set within a peripheral edge portion (1b) of the body (3) and electrically connected to the active region; and a guard region (4b), having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface (3a) and connecting the active region (4a; 29, 30) to the ring region (5). The process further envisages the steps of: forming a surface layer (9) having the first type of conductivity on the first top surface (3a), also at the peripheral edge portion (1b), in contact with the guard region; and etching the surface layer (9) in order to remove it above the edge portion (1b) in such a manner that the etch terminates inside the guard region (4b).

Abstract translation: 一种用于制造半导体功率器件的工艺设想的以下步骤：提供由半导体材料制成的本体（3），其具有第一顶表面（3a）的; 形成于有源区（4a中; 29，30）与所述第一顶表面（3a）的附近的第一导电类型和内部向身体的活性部分（1a）中（3）; 和边缘终端结构的形成（图4b，5）。 边缘终端结构通过以下步骤形成：（5）具有第一导电类型和第一掺杂水平，外围边缘部分内设置一个环区（1b）的所述主体（3）和电连接到所述有源区; 和一个保护区（4b）的具有第一类型导电性的和第二掺杂水平，比所述第一掺杂水平较高，在所述第一顶表面（3a）的附近设置和连接所述有源区（4a中; 29，30 ）到环形区域（5）。 该方法进一步设想如下步骤：形成具有第一顶表面（3a）的所述第一导电类型的表面层（9），所以在周缘部分（1b）中，在与所述保护区接触; 并且为了蚀刻所述表面层（9），以寻求的方式没有蚀刻除去其边缘部分（1b）中上方的防护区域内终止（4b）中。

公开(公告)号：EP1742250A1

公开(公告)日：2007-01-10

申请号：EP05425496.6

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio

IPC: H01L21/04 ,  H01L29/78 ,  H01L29/24 ,  H01L29/423 ,  H01L21/265

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068

Abstract: Method for manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate (10,11) comprising a wide band gap superficial semiconductor layer (11), the method comprising the steps of:
- forming a screening structure (12) on the superficial semiconductor layer (11) comprising at least one dielectric layer (12) which leaves a plurality of areas of the superficial semiconductor layer (11) exposed,
- carrying out at least a first ion implantation of a first type of dopant in the superficial semiconductor layer (11) for forming at least one deep implanted region (14a),
- carrying out at least a second ion implantation of the first type of dopant in the superficial semiconductor layer (11) for forming at least one implanted body region (16) of the MOS transistor aligned with the deep implanted region (14a),
- carrying out at least one ion implantation of a second type of dopant in the superficial semiconductor layer (11) for forming at least an implanted source region (18) of the MOS transistor inside the at least one implanted body region (16), the method comprising an activation thermal process of the first type and second type of low thermal budget dopant suitable to complete said formation of the body region (16), of the source region (18) and of the deep implanted region (14a).

Abstract translation: 一种用于在包括宽带隙表面半导体层（11）的宽带隙半导体衬底（10,11）上制造垂直功率MOS晶体管的方法，所述方法包括以下步骤： - 在表面上形成屏蔽结构（12） 包括至少一个电介质层（12）的半导体层（11），所述至少一个电介质层（12）使所述表面半导体层（11）的多个区域暴露， - 在所述表面半导体层中执行至少第一类型掺杂剂的第一离子注入 （11），用于形成至少一个深注入区域（14a）， - 在所述表面半导体层（11）中执行所述第一类型掺杂物的至少第二离子注入，以形成至少一个注入体区域（16）， 所述MOS晶体管与所述深注入区域（14a）对准， - 在所述表面半导体层（11）中执行至少一次第二类型掺杂物的离子注入，以形成至少一个注入源区域 所述方法包括适于完成所述体区（16）的所述形成的所述第一类型和第二类型低热预算掺杂物的激活热过程， ），源极区域（18）和深注入区域（14a）。

公开(公告)号：EP1710843A1

公开(公告)日：2006-10-11

申请号：EP05425194.7

申请日：2005-04-04

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics S.A.

Inventor： Saggio, Mario Giuseppe ,  Longo Minnolo, Antonino ,  Germana', Rosalia

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L29/0634 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/7803 ,  H01L29/7811

Abstract: The integrated power device comprises a semiconductor body (41, 42) of a first conductivity type comprising a first region (43) accommodating a start-up structure (14), and a second region (44) accommodating a power structure (18). The two structures (14, 18) are separated from one another by an edge structure (30) and are arranged in a mirror configuration with respect to a symmetry line of the edge structure (30). Both the start-up structure (14) and the power structure (18) are obtained using MOSFET devices. More in particular, both MOSFET devices are multi-drain MOSFET devices, having mesh regions (46, 47), source regions (50, 51) and gate regions (60, 61) separated from one another. In addition, both MOSFET devices have drain regions (42a, 42b) delimited by columns (52, 53) that repeat periodically at a fixed distance. Between the two MOSFET devices there is an electrical insulation of at least 25 V.

Abstract translation: 集成功率器件包括第一导电类型的半导体本体（41,42），包括容纳起动结构（14）的第一区域（43）和容纳功率结构（18）的第二区域（44）。 两个结构（14,18）通过边缘结构（30）彼此分离，并且相对于边缘结构（30）的对称线布置成镜子结构。 使用MOSFET器件获得启动结构（14）和功率结构（18）。 更具体地，两个MOSFET器件都是具有网格区域（46,47），源极区域（50,51）和彼此分离的栅极区域（60,61）的多漏极MOSFET器件。 此外，两个MOSFET器件具有由以固定距离周期性重复的列（52,53）限定的漏极区域（42a，42b）。 在两个MOSFET器件之间存在至少25V的电绝缘。

公开(公告)号：EP1696490A1

公开(公告)日：2006-08-30

申请号：EP05425102.0

申请日：2005-02-25

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio

IPC: H01L29/78

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095

Abstract: Compensation power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity comprising a plurality of elemental units, each elemental unit comprising:

a body region (40) of a second type of conductivity realised on a semiconductor layer (20) of the first type of conductivity formed on the semiconductor substrate (100),
a column region (50) of the second type of conductivity realised in said semiconductor layer (20) below the body region (40),

wherein the semiconductor layer (20) comprises a plurality of semiconductor layers (21,22,23,24), overlapped on each other, wherein the resistivity of each layer is different from that of the other layers and in that said column region (50) comprises a plurality of doped sub-regions (51,52,53,54), each realised in one of said semiconductor layers (21,22,23,24), wherein the dopant concentration of each doped sub-region (51,52,53,54) is such as to realise a balance between the total amount of charge of a first conductivity type and of a second conductivity type in each couple of layers and subregions.

Abstract translation: 集成在包括多个元件单元的第一导电类型的半导体衬底（100）上的补偿电力电子器件（30），每个元件单元包括：在半导体层上实现的第二导电类型的体区（40） 在所述半导体衬底（100）上形成的所述第一类型导电体的导体（20），在所述半导体层（20）中实现的所述第二导电类型的列区域（50），其中所述半导体层 （20）包括彼此重叠的多个半导体层（21,22,23,24），其中每个层的电阻率不同于其它层的电阻率，并且所述列区域（50）包括多个 的掺杂子区域（51,52,53,54），其分别在所述半导体层（21,22,23,24）中的一个中实现，其中每个掺杂子区域（51,52,53， 54）实现了af的总费用之间的平衡 第一导电类型和第二导电类型在每对层和子区域。