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    Shielded coplanar line
    14.
    发明授权
    Shielded coplanar line 有权
    屏蔽共面线

    公开(公告)号：US09324612B2

    公开(公告)日：2016-04-26

    申请号：US13899326

    申请日：2013-05-21

    Applicant: STMicroelectronics SA

    Inventor： Sylvain Joblot ,  Pierre Bar

    IPC: H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01P3/00 ,  H01P11/00

    CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01P3/003 ,  H01P3/006 ,  H01P11/003 ,  H01L2924/00

    Abstract: In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.

    Abstract translation: 在一个实施例中，公开了一种用于在包括通孔和共面线的半导体衬底中制造集成电路的方法，包括以下步骤：形成有源部件和一组前金属化层; 同时从衬底a的后表面通过通孔和穿过衬底穿过其高度的至少50％的沟槽; 用导电材料涂覆壁和孔的底部和沟槽; 并用绝缘填充材料填充孔和沟槽; 并且在沟槽的前面并与其平行地形成在衬底的后表面上延伸的共面线，使得共面线的横向导体电连接到涂覆沟槽的壁的导电材料。

    PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING AT LEAST ONE COPLANAR WAVEGUIDE
    15.
    发明申请
    PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING AT LEAST ONE COPLANAR WAVEGUIDE 审中-公开
    用于制造包含至少一个共振波导的集成电路的方法

    公开(公告)号：US20160097898A1

    公开(公告)日：2016-04-07

    申请号：US14970792

    申请日：2015-12-16

    Applicant: STMicroelectronics SA

    Inventor： Sylvain Joblot ,  Pierre Bar

    IPC: G02B6/12 ,  H01L21/48 ,  H01L21/768

    CPC classification number: H01L21/76831 ,  G02B6/12 ,  H01L21/4846 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/66 ,  H01P11/003

    Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

    Abstract translation: 集成电路包括绝缘体上硅晶片和互连层，其为在支撑体的顶侧上方形成的共面波导提供支撑。 穿通硅通孔由支撑体的背面形成并穿过绝缘体上硅晶片以到达互连层。 从共面波导下方的支撑体的背面形成沟槽。 沟槽在共面波导的至少整个长度上延伸。 沟槽穿过绝缘体上硅晶片以到达互连层，并且可以具有与穿硅通孔基本相同的深度。

    SHIELDED COPLANAR LINE
    16.
    发明申请
    SHIELDED COPLANAR LINE 有权
    屏蔽共振线

    公开(公告)号：US20130313724A1

    公开(公告)日：2013-11-28

    申请号：US13899326

    申请日：2013-05-21

    Applicant: STMicroelectronics SA

    Inventor： Sylvain Joblot ,  Pierre Bar

    IPC: H01L21/768 ,  H01L23/48

    CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01P3/003 ,  H01P3/006 ,  H01P11/003 ,  H01L2924/00

    Abstract: In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.

    Abstract translation: 在一个实施例中，公开了一种用于在包括通孔和共面线的半导体衬底中制造集成电路的方法，包括以下步骤：形成有源部件和一组前金属化层; 同时从衬底a的后表面通过通孔和穿过衬底穿过其高度的至少50％的沟槽; 用导电材料涂覆壁和孔的底部和沟槽; 并用绝缘填充材料填充孔和沟槽; 并且在沟槽的前面并与其平行地形成在衬底的后表面上延伸的共面线，使得共面线的横向导体电连接到涂覆沟槽的壁的导电材料。

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