公开(公告)号：EP2299450A1

公开(公告)日：2011-03-23

申请号：EP09425360.6

申请日：2009-09-18

Applicant: STMicroelectronics Srl

Inventor： Lo Giudice, Gianbattista ,  Conte, Antonino ,  Micciche', Mario ,  Rinaldi, Stefania

IPC: G11C16/28 ,  G11C7/06 ,  G11C7/02 ,  G11C7/12

CPC classification number: G11C16/28 ,  G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C2207/063

Abstract: A sense-amplifier circuit (1) for a non-volatile memory is provided with: a comparison stage (15, 16a-16b) that executes, during a comparison step, a comparison between a cell current (I cell ) that flows in a memory cell (2) and through an associated bitline (BL), and a reference current (I raf ), for supplying an output signal (Out sense) indicating the state of the memory cell (2); and a precharging stage (18a-18b, 22a-22b), which supplies, during a precharging step prior to the comparison step, a precharging current to the bitline (BL) so as to charge a capacitance thereof; the comparison stage is formed by a first comparison transistor (16a) and by a second comparison transistor (16b), which are coupled in current-mirror configuration respectively to a first differential output (Out1) and to a second differential output (Out2), through which a biasing current flows. The precharging stage diverts, during the precharging step, the biasing current towards the bitline (BL) as precharging current, and allows, during the comparison step, passage of part of the biasing current towards the first differential output, enabling operation of the current mirror.

Abstract translation: 用于非易失性存储器中的读出放大器电路（1）被提供有：在比较步骤没有执行比较阶段（15，16A-16B），一个单元电流（I小区）之间的比较中没有流 存储器单元（2），并通过向相关联的位线（BL），和一个参考电流（I REF），用于提供给输出信号（OUT感）指示的存储单元（2）的状态; 和预充电阶段（图18A-18B，22A-22B），它提供，在之前的比较步骤中，预充电电流提供给位线（BL），以便它们的充电电容的预充电步骤; 比较级由第一比较晶体管（16A）和由第二比较晶体管（16B），它们分别耦合在电流镜配置，以第一差分输出（OUT1）以及第二差分输出（OUT2）而形成 其通过偏置电流流过。 在预充电阶段转接，在预充电步骤，向位线（BL）作为预充电电流的偏置电流，并且允许，在比较步骤中，朝向所述第一差分输出的偏置电流的一部分流路，从而使操作所述电流镜的 ，

公开(公告)号：EP2320296B1

公开(公告)日：2012-12-05

申请号：EP10189494.7

申请日：2010-10-29

Applicant: STMicroelectronics Srl

Inventor： Conte, Antonino ,  Micciche', Mario ,  Giaquinta, Maria ,  Grasso, Rosario Roberto

IPC: G05F3/30 ,  H03F3/347

CPC classification number: G05F3/30 ,  H03F3/347 ,  H03F3/45183 ,  H03F2203/45466

公开(公告)号：EP2320295B1

公开(公告)日：2012-12-05

申请号：EP10189487.1

申请日：2010-10-29

Applicant: STMicroelectronics Srl

Inventor： Conte, Antonino ,  Micciche', Mario ,  Grasso, Rosario Roberto ,  Giaquinta, Maria

IPC: G05F3/30 ,  H03F3/393

CPC classification number: G05F3/30 ,  H03F3/347 ,  H03F3/45183 ,  H03F2203/45466

公开(公告)号：EP2302635A1

公开(公告)日：2011-03-30

申请号：EP09425359.8

申请日：2009-09-18

Applicant: STMicroelectronics Srl

Inventor： Lo Giudice, Gianbattista ,  Castaldo, Enrico ,  Conte, Antonino

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/0433 ,  G11C16/10 ,  G11C16/16

Abstract: Described herein is a method for biasing an EEPROM array (10) formed by memory cells (2) arranged in rows and columns, each operatively coupled to a first switch (3) and to a second switch (4) and having a first current-conduction terminal selectively connectable to a bitline (BL) through the first switch (3) and a control terminal selectively connectable to a gate-control line (Cgt) through the second switch (4), wherein associated to each row are a first wordline (WL seltr) and a second wordline (WL bsw), connected to the control terminals of the first switches (3) and, respectively, of the second switches (4) operatively coupled to the memory cells (2) of the same row. The method envisages selecting at least one memory cell (2) for a given memory operation, biasing the first wordline and the second wordline of the row associated thereto, and in particular biasing the first and second wordlines with voltages different from one another and having values that are higher than an internal supply voltage (V DD ) and are a function of the given memory operation.

Abstract translation: 在描述了一种用于EEPROM阵列的偏压（10）的存储单元（2）形成排列成行和列，每个可操作地耦合到第一开关的方法（3）和第二开关（4），并具有第一电流 - 导通端子选择性地连接到穿过所述第二开关与第一开关（3）和控制端子选择性地连接到栅极控制线（CGT）的位线（BL）（4），相关联的各行worin是第一字线（ WL seltr）和第二字线（WL BSW），分别连接到第一开关（3）和，的控制端子，所述第二开关（4），其可操作地耦合到同一行的存储单元（2）。 该方法设想选择至少一个存储单元（2）对于给定的存储器操作，偏置第一字线和列与其相关联的第二个字线，且在特定偏置与彼此和具有值的不同电压下的第一和第二字线 并比内部电源电压（V DD）和更高的给定的存储器操作的功能。