Abstract:
An interface system (10) for interfacing an asynchronous circuit with a synchronous circuit, wherein the synchronous circuit samples, in response to a clock signal (CLK RX), a first data signal (DATA) when a first control signal (REQ) indicates that the first data signal (DATA) contains valid data, and wherein the asynchronous circuit (4) generates a second data signal (ADATA) according to an asynchronous communication protocol. In particular, the system comprises: - a First-In First-Out memory (18) comprising a plurality of memory locations, - a control circuit (20) configured for: a) asynchronously writing (204, 206) the second data signal (ADATA) in the memory (18) when the second data signal (ADATA) indicates the start of a communication, and b) synchronously reading (200, 202) the second data signal (ADATA') from the memory (18) in response to a clock signal (CLK_RX),
- a conversion circuit (12) configured for decoding, according to a asynchronous communication protocol, the second data signal (ADATA') read from the memory (18) in a decoded data signal, wherein the decoded data signal corresponds to the first data signal (DATA).
Abstract:
A communication system for interfacing a first synchronous circuit (1) with a second synchronous circuit (6). The system comprising a first interface system (3) and a second interface system (5). The first interface system (3) receives data (TX_DATA) from the first synchronous circuit (1), and encodes (32) the data (TX_DATA) according to an asynchronous communication protocol. The encoded data (ADATA) are transmitted over a communication channel to the second interface system (5). The second interface system (5) decodes the data (ADATA) and transmits the decoded data (RX_DATA) to the second synchronous circuit (6). In particular, the first interface system (3) comprises a first First-In First-Out memory for storing temporarily the data (TX_DATA) received from the first synchronous circuit (1) and the second interface system (5) comprises a second First-In First-Out memory for storing temporarily the data (ADATA) transmitted over the communication channel, and the communication system is configured for transmitting to the first synchronous circuit (1) a control signal (TX_ACK') determined (310) as a function of the state of the first and the second memory.
Abstract:
An interface system (10) for interfacing a synchronous circuit with an asynchronous circuit, wherein the synchronous circuit generates, in response to a clock signal (CLK TX), a first control signal (REQ) indicating the fact that a first data signal (DATA) contains valid data, and wherein the asynchronous circuit (4) generates, according to an asynchronous communication protocol, a second control signal (AACK) indicating the state of transmission of a second data signal (ADATA). In particular, the system comprises: - a conversion circuit (12), configured for converting, according to the asynchronous communication protocol, the first data signal (DATA) into an encoded data signal (ADATA'), - a First-in First-out memory (18) comprising a plurality of memory locations, wherein the signal currently read from the memory (18) corresponds to the second data signal (ADATA), and - a control circuit configured for: a) writing the encoded data signal (ADATA') in the memory (18) in a synchronous way in response to the clock signal (CLK TX), and b) reading the second data signal (ADATA) from the memory (18) in an asynchronous way in response to the second control signal (AACK).