Abstract:
A package comprising a first die; a second die; an interface connecting said first die and said second die, at least one of said first and second dies comprising a memory, said interface being configured to transport both control signals and memory transactions; and multiplexing means for multiplexing said control signals and said memory transactions onto said interface such that a plurality of connections of said interface are shared by said control signals and said memory transactions.
Abstract:
An arrangement comprises an input configured to receive data; and at least one multiplexer configured to receive a first logic level at a first input and a second logic level at a second level, at least a part of said data being received at a control input of said multiplexer.
Abstract:
An arrangement comprising a plurality of data stores, each data store being configured to store data, and a controller arranged to selectively apply a clock signal to said respective data stores.
Abstract:
A circuit comprises a first Muller gate having a first input configured to receive a clock signal, a second input configured to receive an enable signal and an output. A logic circuit is also provided having a first input configured to receive said clock signal, and a second input configured to receive an input dependent on said output, said logic circuit being configured to provide a gated clock output.
Abstract:
A method of perform transactions in a communication network, wherein information is exchanged between Intellectual Property (IP) cores. The information is transported in packets (P) including a header (HD) for transporting control information, and one or more payloads (PL) transporting content. The method provide the use of a versatile packet format (HF1-HF17) adapted to transport different traffic patterns generated by Intellectual Property (IP) cores using different protocols to ensure a simple interoperability between the Intellectual Property (IP) cores, providing also the configurability of the granularity arbitration process in order to correct crossing the routers in the communication network.
Abstract:
A data serializer comprising an input configured to receive a plurality of sets of parallel data, each set of data comprising n bits and at least one serializing stage configured to receive a set of n bits of parallel data and to convert said parallel data to a serial stream of data, said at least one serializing stage comprising a chain of flip flops each of which is arranged to selectively receive one of a bit of data and data output from a preceding flip flop, an output of a last flip flop of said chain of flip flops providing said serial stream of data.