公开(公告)号：EP1009162A2

公开(公告)日：2000-06-14

申请号：EP99309801.1

申请日：1999-12-07

Applicant: STMicroelectronics, Inc.

Inventor： McDade, Darryn ,  Owen, Jefferson Eugene

IPC: H04N5/00

CPC classification number: H04N19/44 ,  G11B20/10 ,  G11B27/105 ,  G11B2220/2562 ,  H04N21/40

Abstract: The present invention provides a system and an apparatus for a digital audio/video decoder comprising a file reader capable of obtaining an encoded audio/video data stream from a data source, a navigator that instructs the file reader to obtain the encoded audio/video data stream, a splitter that separates the encoded audio/video data stream obtained by the file reader into one or more component data streams, and a reprogrammable proxy filter that decodes and converts the one or more component data streams into three or more renderable signals including at least one renderable audio signal and at least two renderable video signals.

Abstract translation: 本发明提供了一种用于数字音频/视频解码器的系统和装置，包括能够从数据源获得编码的音频/视频数据流的文件读取器，指导文件读取器获得编码音频/视频数据的导航器 流，分离器，将由文件读取器获得的编码音频/视频数据流分离成一个或多个分量数据流;以及可重编程代理滤波器，其将一个或多个分量数据流解码并转换为三个或更多个可渲染信号，包括在 至少一个可渲染音频信号和至少两个可渲染视频信号。

公开(公告)号：EP2015505A2

公开(公告)日：2009-01-14

申请号：EP08012447.2

申请日：2008-07-10

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Bertoni, Guido Marco ,  Owen, Jefferson Eugene

IPC: H04L9/06

CPC classification number: H04L9/0637 ,  G09C1/00 ,  H04L2209/122 ,  H04L2209/125

Abstract: An encoding/decoding apparatus comprises a central processing unit and an encryption/decryption accelerator coupled to the central processing unit The accelerator comprises an input for input data to be encrypted/decrypted, an arithmetic logic unit coupled to said input for performing selectable operations on data obtained from said input data and an output for encrypted/decrypted data coupled to said arithmetic logic unit.

Abstract translation: 编码/解码装置包括中央处理单元和耦合到中央处理单元的加密/解密加速器。加速器包括用于要加密/解密的输入数据的输入，耦合到所述输入的算术逻辑单元，用于对数据进行可选择的操作 从所述输入数据获得的输出和与所述算术逻辑单元耦合的加密/解密数据的输出。

公开(公告)号：EP1024668A1

公开(公告)日：2000-08-02

申请号：EP99309803.7

申请日：1999-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Owen, Jefferson Eugene ,  McDade, Darryn

IPC: H04N7/50

CPC classification number: H04N19/43 ,  H04N19/51

Abstract: The present invention provides a method and an apparatus for an instruction generator that utilizes two or more parameters comprising one or more prediction mode parameters and one or more motion vector parameters to generate one or more motion compensation instructions for a prediction block in a macroblock.

Abstract translation: 本发明提供了一种用于指令生成器的方法和装置，其利用包括一个或多个预测模式参数和一个或多个运动矢量参数的两个或多个参数来生成用于宏块中的预测块的一个或多个运动补偿指令。

公开(公告)号：EP0847203A3

公开(公告)日：2000-03-08

申请号：EP97309486.5

申请日：1997-11-25

Applicant: STMicroelectronics, Inc.

Inventor： Owen, Jefferson Eugene ,  Balakrishnan, Jeyendran

IPC: H04N7/50

CPC classification number: H04N19/428 ,  H04N19/423 ,  H04N19/61

Abstract: A method of reducing the memory required for decompression of a compressed frame by storing frame in a compressed format using DCT based techniques and decoders for implementing such a method are disclosed. The decoder is coupled to a memory where the frame can be stored. The decoder includes a decoder module having a parser, a block decoder module and a motion compensation engine. The decoder module is coupled to a DCT encoder module, which has an output coupled to the memory. The decoder also includes a stored DCT decoder module, which has an input coupled to the memory, a first output coupled to the motion compensation module and a second output that functions as an output of the decoder.

公开(公告)号：EP1715696B1

公开(公告)日：2019-12-11

申请号：EP06076530.2

申请日：1999-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Owen, Jefferson Eugene ,  McDade, Darryn

IPC: H04N19/51 ,  H04N19/61 ,  H04N19/43 ,  H04N19/44

公开(公告)号：EP1009170B1

公开(公告)日：2009-04-15

申请号：EP99309802.9

申请日：1999-12-07

Applicant: STMicroelectronics, Inc.

Inventor： McDade, Darryn ,  Owen, Jefferson Eugene

IPC: H04N7/36

CPC classification number: H04N19/43 ,  H04N19/44 ,  H04N19/51 ,  H04N19/61

公开(公告)号：EP1715696A3

公开(公告)日：2008-03-19

申请号：EP06076530.2

申请日：1999-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Owen, Jefferson Eugene ,  McDade, Darryn

IPC: H04N7/36

Abstract: A digital video decoder comprising a bit unpacker that utilizes at least an encoded video data stream to produce a prediction data stream and a coding data stream; a motion compensation instruction encoder communicably coupled to the bit unpacker, the motion compensation instruction encoder utilizing at least the prediction data stream to selectively produce a set of motion compensation instructions; and a block decoder communicably coupled to the bit unpacker, the block decoder utilizing at least the coding data stream to produce a set of error terms.

公开(公告)号：EP1024668B1

公开(公告)日：2006-05-24

申请号：EP99309803.7

申请日：1999-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Owen, Jefferson Eugene ,  McDade, Darryn

IPC: H04N7/50

CPC classification number: H04N19/43 ,  H04N19/51

公开(公告)号：EP1009170A2

公开(公告)日：2000-06-14

申请号：EP99309802.9

申请日：1999-12-07

Applicant: STMicroelectronics, Inc.

Inventor： McDade, Darryn ,  Owen, Jefferson Eugene

IPC: H04N7/36

CPC classification number: H04N19/43 ,  H04N19/44 ,  H04N19/51 ,  H04N19/61

Abstract: The present invention provides a system, method and an apparatus for a digital video decoder, which includes a data processor that utilizes at least an encoded video data stream to produce one or more output streams. The one or more output streams includes at least a set of motion compensation instructions.

Abstract translation: 本发明提供了一种用于数字视频解码器的系统，方法和装置，其包括利用至少编码视频数据流来产生一个或多个输出流的数据处理器。 一个或多个输出流包括至少一组运动补偿指令。

公开(公告)号：EP1009169A2

公开(公告)日：2000-06-14

申请号：EP99309800.3

申请日：1999-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Owen, Jefferson Eugene ,  McDade, Darryn

IPC: H04N7/36 ,  H04N7/50

CPC classification number: H04N19/523

Abstract: The present invention provides a system, method and an apparatus for a digital video processor comprising an error memory and a merge memory, a half pixel filter communicably coupled to the merge memory, a controller communicably coupled to the error memory, the merge memory and the half pixel filter. The present invention also including a sum unit communicably coupled to the error memory. The controller executing one or more instructions to provide motion compensation during video decoding.

Abstract translation: 本发明提供了一种用于数字视频处理器的系统，方法和装置，包括错误存储器和合并存储器，可通信地耦合到合并存储器的半像素滤波器，可通信地耦合到错误存储器的控制器，合并存储器和 半像素滤光片 本发明还包括可通信地耦合到错误存储器的总和单元。 所述控制器执行一个或多个指令以在视频解码期间提供运动补偿。