公开(公告)号：EP1086425A1

公开(公告)日：2001-03-28

申请号：EP99928643.8

申请日：1999-06-14

Applicant: SUN MICROSYSTEMS, INC.

Inventor： GARNETT, Paul, J. ,  ROWLINSON, Stephen ,  OYELAKIN, Femi, A.

IPC: G06F11/22 ,  G06F13/40

CPC classification number: G06F11/2289 ,  G06F13/404

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set, and a device bus. A bridge control mechanism is configured to provide geographic addressing for devices on the device bus and to be responsive to a request from a device on the device bus for direct access to a resource of a processing set to verify that an address supplied by the device falls within a correct geographic range. A different geographic address range can be allocated to each of a plurality of device slots on the device bus. A different geographic address range can also be allocated to the processor set resources (e.g., processor set memory). An address decoding mechanism maintains geographic address mappings, and verifies geographic addresses for direct memory access. The geographic address mappings can be configured in random access memory of the bridge. A slot response register is associated with each slot on the device bus. The slot response register records ownership of a device by the processing sets. The bridge control mechanism responds to a direct memory access request from a device on the device bus to access the slot response register for the slot for the requesting device for identifying the owning processor set, for enabling access to the memory of the owning processor set. The slot response registers can be configured in random access memory in the bridge.

公开(公告)号：EP1145131B1

公开(公告)日：2004-08-18

申请号：EP99928406.0

申请日：1999-06-04

Applicant: Sun Microsystems, Inc.

Inventor： ROWLINSON, Stephen ,  OYELAKIN, Femi, A. ,  WILLIAMS, Emrys, J. ,  GARNETT, Paul, J.

IPC: G06F13/40

CPC classification number: G06F13/4027

Abstract: A bridge for a computer system comprising at least a first processing set and a second processing set each connected to the bridge via an I/O bus. A resource control mechanism in the bridge comprises: an interface for exchanging signals with one or more resource slots of a device bus that is capable of being connected to the bridge, each of the resource slots being capable of communicating with a system resource; and a register associated with each system resource, the register having switchable indicia that indicate an operating state of the associated system resource, the control mechanism being operable in use to direct signals to and/or from respective system resources of the computer system.

公开(公告)号：EP1088272B1

公开(公告)日：2002-10-23

申请号：EP99928544.8

申请日：1999-06-09

Applicant: SUN MICROSYSTEMS, INC.

Inventor： ROWLINSON, Stephen ,  OYELAKIN, Femi, A. ,  GARNETT, Paul J.

IPC: G06F11/16 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F11/1641 ,  G06F11/1658 ,  G06F11/1683 ,  G06F13/4036 ,  G06F2201/845

Abstract: A bridge for a multi-processor system provides interfaces to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism arbitrates between the first and the second processing sets for access to each others I/O bus and to the device bus in a first, split, mode, and monitors lockstep operation of the first and second processing sets in a second, combined, mode. On detecting a lockstep error in the combined mode, the bridge transfers to an error mode. The bridge control mechanism buffers write accesses in a posted write buffer in the error mode pending resolution of the error.

公开(公告)号：EP1090350B1

公开(公告)日：2002-04-10

申请号：EP99926161.3

申请日：1999-06-03

Applicant: SUN MICROSYSTEMS, INC.

Inventor： ROWLINSON, Stephen ,  OYELAKIN, Femi, A. ,  GARNETT, Paul J.

IPC: G06F11/16 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F11/1658 ,  G06F11/004 ,  G06F11/1625 ,  G06F11/2268 ,  G06F13/4027

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. It also comprises a bridge control mechanism configured to be operable, in an operational mode to permit access by at least one of the first and second processing sets to bridge resources and to the device bus and, in an error mode, to prevent access by the processing sets to the device bus and to permit restricted access to at least one of the processing sets to at least predetermined bridge resources. By providing restricted access to selected parameters held in the bridge during an error mode, the bridge can act as a secure repository for information which can be used by the processing sets to investigate the error and hopefully to recover therefrom, while preventing I/O devices connected to device bus from being corrupted by a faulty processing set. Storage in the bridge provides for buffering data pending resolution of the error.

公开(公告)号：EP1086425B1

公开(公告)日：2002-04-10

申请号：EP99928643.8

申请日：1999-06-14

Applicant: SUN MICROSYSTEMS, INC.

Inventor： GARNETT, Paul, J. ,  ROWLINSON, Stephen ,  OYELAKIN, Femi, A.

IPC: G06F11/22 ,  G06F13/40

CPC classification number: G06F11/2289 ,  G06F13/404

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set, and a device bus. A bridge control mechanism is configured to provide geographic addressing for devices on the device bus and to be responsive to a request from a device on the device bus for direct access to a resource of a processing set to verify that an address supplied by the device falls within a correct geographic range. A different geographic address range can be allocated to each of a plurality of device slots on the device bus. A different geographic address range can also be allocated to the processor set resources (e.g., processor set memory). An address decoding mechanism maintains geographic address mappings, and verifies geographic addresses for direct memory access. The geographic address mappings can be configured in random access memory of the bridge. A slot response register is associated with each slot on the device bus. The slot response register records ownership of a device by the processing sets. The bridge control mechanism responds to a direct memory access request from a device on the device bus to access the slot response register for the slot for the requesting device for identifying the owning processor set, for enabling access to the memory of the owning processor set. The slot response registers can be configured in random access memory in the bridge.

公开(公告)号：EP1145131A3

公开(公告)日：2002-03-27

申请号：EP99928406.0

申请日：1999-06-04

Applicant: SUN MICROSYSTEMS, INC.

Inventor： ROWLINSON, Stephen ,  OYELAKIN, Femi, A. ,  WILLIAMS, Emrys, J. ,  GARNETT, Paul, J.

IPC: G06F13/40

CPC classification number: G06F13/4027

公开(公告)号：EP1145131A2

公开(公告)日：2001-10-17

申请号：EP99928406.0

申请日：1999-06-04

Applicant: SUN MICROSYSTEMS, INC.

Inventor： ROWLINSON, Stephen ,  OYELAKIN, Femi, A. ,  WILLIAMS, Emrys, J. ,  GARNETT, Paul, J.

IPC: G06F13/40

CPC classification number: G06F13/4027

Abstract: A bridge for a computer system comprising at least a first processing set and a second processing set each connected to the bridge via an I/O bus. A resource control mechanism in the bridge comprises: an interface for exchanging signals with one or more resource slots of a device bus that is capable of being connected to the bridge, each of the resource slots being capable of communicating with a system resource; and a register associated with each system resource, the register having switchable indicia that indicate an operating state of the associated system resource, the control mechanism being operable in use to direct signals to and/or from respective system resources of the computer system.