公开(公告)号：EP1090349B1

公开(公告)日：2002-02-20

申请号：EP99926160.5

申请日：1999-06-03

Applicant: SUN MICROSYSTEMS, INC.

Inventor： ROWLINSON, Stephen ,  OYELAKIN, Femi, A. ,  WILLIAMS, Emrys, J. ,  GARNETT, Paul, J.

IPC: G06F11/16 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F11/1658 ,  G06F11/1641 ,  G06F11/1683 ,  G06F13/4027 ,  G06F2201/845

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism is configured to compare address and data phases of I/O accesses by the first and second processing sets. At least one dissimilar data register is provided for each processing set. The bridge control mechanism is operable in response to an address phase of a dissimilar data register write access to disregard any differences in the data phase for the dissimilar data write access. Non-deterministic data (for example relating to a real time clock) can be output from the processing sets in a combined (lockstep comparison) mode. A read destination address supplied in common by the first and second processing sets for a dissimilar data read access can cause data read from a determined one of the dissimilar data registers to be supplied the first and second processing sets. In this manner, the processing sets may have the dissimilar data replaced by the same data. The read destination address supplied in common by the first and second processing sets can determine the dissimilar data register from which data is read.

公开(公告)号：EP1088273A1

公开(公告)日：2001-04-04

申请号：EP99930146.8

申请日：1999-06-04

Applicant: SUN MICROSYSTEMS, INC.

Inventor： GARNETT, Paul J. ,  ROWLINSON, Stephen ,  OYELAKIN, Femi, A.

IPC: G06F11/16 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F11/1641 ,  G06F11/1625 ,  G06F11/165 ,  G06F11/1658 ,  G06F13/4027

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. The bridge also includes a memory subsystem and a bridge control mechanism. The bridge control mechanism is operable to monitor operation of the first and second processing sets in a combined, lockstep, operating mode and to be responsive to detection of a lockstep error to cause the bridge to be operable in an error mode in which write accesses initiated by the processor sets are buffered in a bridge buffer pending resolution of the error mode. A respective buffer region is provided for each processing set. In an initial error mode, any complete device write accesses initiated by the processing sets are stored in a posted write buffer. Where data is in transit through the bridge on entry to the error mode, the data is diverted to one or more disconnect registers. The bridge control mechanism is operable to permit read access to the posted write buffers and the disconnect registers by the processing sets to enable recovery from the error mode.

公开(公告)号：EP1086424B1

公开(公告)日：2002-02-27

申请号：EP99957102.9

申请日：1999-06-03

Applicant: SUN MICROSYSTEMS, INC.

Inventor： ROWLINSON, Stephen ,  OYELAKIN, Femi, A. ,  GARNETT, Paul J.

IPC: G06F11/16 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F11/1658 ,  G06F11/1641 ,  G06F11/1683 ,  G06F13/4027 ,  G06F2201/845

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism is configured to compare address and data phases of I/O accesses by the first and second processing sets. At least one dissimilar data register is provided for each processing set. The bridge control mechanism is operable in response to an address phase of a dissimilar data register write access to disregard any differences in the data phase for the dissimilar data write access. Non-deterministic data (for example relating to a real time clock) can be output from the processing sets in a combined (lockstep comparison) mode. A read destination address supplied in common by the first and second processing sets for a dissimilar data read access can cause data read from a determined one of the dissimilar data registers to be supplied the first and second processing sets. In this manner, the processing sets may have the dissimilar data replaced by the same data. The read destination address supplied in common by the first and second processing sets can determine the dissimilar data register from which data is read.

公开(公告)号：EP1090350A1

公开(公告)日：2001-04-11

申请号：EP99926161.3

申请日：1999-06-03

Applicant: SUN MICROSYSTEMS, INC.

Inventor： ROWLINSON, Stephen ,  OYELAKIN, Femi, A. ,  GARNETT, Paul J.

IPC: G06F11/16 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F11/1658 ,  G06F11/004 ,  G06F11/1625 ,  G06F11/2268 ,  G06F13/4027

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. It also comprises a bridge control mechanism configured to be operable, in an operational mode to permit access by at least one of the first and second processing sets to bridge resources and to the device bus and, in an error mode, to prevent access by the processing sets to the device bus and to permit restricted access to at least one of the processing sets to at least predetermined bridge resources. By providing restricted access to selected parameters held in the bridge during an error mode, the bridge can act as a secure repository for information which can be used by the processing sets to investigate the error and hopefully to recover therefrom, while preventing I/O devices connected to device bus from being corrupted by a faulty processing set. Storage in the bridge provides for buffering data pending resolution of the error.

公开(公告)号：EP1090349A1

公开(公告)日：2001-04-11

申请号：EP99926160.5

申请日：1999-06-03

Applicant: SUN MICROSYSTEMS, INC.

Inventor： ROWLINSON, Stephen ,  OYELAKIN, Femi, A. ,  WILLIAMS, Emrys, J. ,  GARNETT, Paul, J.

IPC: G06F11/16 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F11/1658 ,  G06F11/1641 ,  G06F11/1683 ,  G06F13/4027 ,  G06F2201/845

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism is configured to compare address and data phases of I/O accesses by the first and second processing sets. At least one dissimilar data register is provided for each processing set. The bridge control mechanism is operable in response to an address phase of a dissimilar data register write access to disregard any differences in the data phase for the dissimilar data write access. Non-deterministic data (for example relating to a real time clock) can be output from the processing sets in a combined (lockstep comparison) mode. A read destination address supplied in common by the first and second processing sets for a dissimilar data read access can cause data read from a determined one of the dissimilar data registers to be supplied the first and second processing sets. In this manner, the processing sets may have the dissimilar data replaced by the same data. The read destination address supplied in common by the first and second processing sets can determine the dissimilar data register from which data is read.

公开(公告)号：EP1086424A1

公开(公告)日：2001-03-28

申请号：EP99957102.9

申请日：1999-06-03

Applicant: SUN MICROSYSTEMS, INC.

Inventor： ROWLINSON, Stephen ,  OYELAKIN, Femi, A. ,  GARNETT, Paul J.

IPC: G06F11/16 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F11/1658 ,  G06F11/1641 ,  G06F11/1683 ,  G06F13/4027 ,  G06F2201/845

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism is configured to compare address and data phases of I/O accesses by the first and second processing sets. At least one dissimilar data register is provided for each processing set. The bridge control mechanism is operable in response to an address phase of a dissimilar data register write access to disregard any differences in the data phase for the dissimilar data write access. Non-deterministic data (for example relating to a real time clock) can be output from the processing sets in a combined (lockstep comparison) mode. A read destination address supplied in common by the first and second processing sets for a dissimilar data read access can cause data read from a determined one of the dissimilar data registers to be supplied the first and second processing sets. In this manner, the processing sets may have the dissimilar data replaced by the same data. The read destination address supplied in common by the first and second processing sets can determine the dissimilar data register from which data is read.

公开(公告)号：EP1088273B1

公开(公告)日：2002-04-10

申请号：EP99930146.8

申请日：1999-06-04

Applicant: SUN MICROSYSTEMS, INC.

Inventor： GARNETT, Paul J. ,  ROWLINSON, Stephen ,  OYELAKIN, Femi, A.

IPC: G06F11/16 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F11/1641 ,  G06F11/1625 ,  G06F11/165 ,  G06F11/1658 ,  G06F13/4027

公开(公告)号：EP1088271B1

公开(公告)日：2002-02-20

申请号：EP99926162.1

申请日：1999-06-03

Applicant: SUN MICROSYSTEMS, INC.

Inventor： ROWLINSON, Stephen ,  OYELAKIN, Femi A. ,  GARNETT, Paul J.

IPC: G06F11/16 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F11/1641 ,  G06F11/1616 ,  G06F11/1658 ,  G06F13/4004 ,  G06F2201/845

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism is operable to compare address and data phases of I/O accesses by the first and second processing sets. A direct memory access mechanism is operable to initiate a direct memory access operation to read from a corresponding location in each processor set into a respective dissimilar data register associated with each processing set. The bridge control mechanism is operable during the direct memory access operation to disregard differences in the data phase for the dissimilar data write access. As a result it is possible to transfer dissimilar data from the processors into the bridge in a combined (lockstep comparison) mode. In a subsequent phase the bridge control mechanism responds to a read destination address supplied in common by the first and second processing sets for a dissimilar data read access to supply data read from a determined one of the dissimilar data registers to the first and second processing sets. In this manner the data from one processing set can be copied to the other processing set while in a combined mode.

公开(公告)号：EP1088272A1

公开(公告)日：2001-04-04

申请号：EP99928544.8

申请日：1999-06-09

Applicant: SUN MICROSYSTEMS, INC.

Inventor： ROWLINSON, Stephen ,  OYELAKIN, Femi, A. ,  GARNETT, Paul J.

IPC: G06F11/16 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F11/1641 ,  G06F11/1658 ,  G06F11/1683 ,  G06F13/4036 ,  G06F2201/845

Abstract: A bridge for a multi-processor system provides interfaces to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism arbitrates between the first and the second processing sets for access to each others I/O bus and to the device bus in a first, split, mode, and monitors lockstep operation of the first and second processing sets in a second, combined, mode. On detecting a lockstep error in the combined mode, the bridge transfers to an error mode. The bridge control mechanism buffers write accesses in a posted write buffer in the error mode pending resolution of the error.

公开(公告)号：EP1088271A1

公开(公告)日：2001-04-04

申请号：EP99926162.1

申请日：1999-06-03

Applicant: SUN MICROSYSTEMS, INC.

Inventor： ROWLINSON, Stephen ,  OYELAKIN, Femi A. ,  GARNETT, Paul J.

IPC: G06F11/16 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F11/1641 ,  G06F11/1616 ,  G06F11/1658 ,  G06F13/4004 ,  G06F2201/845

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism is operable to compare address and data phases of I/O accesses by the first and second processing sets. A direct memory access mechanism is operable to initiate a direct memory access operation to read from a corresponding location in each processor set into a respective dissimilar data register associated with each processing set. The bridge control mechanism is operable during the direct memory access operation to disregard differences in the data phase for the dissimilar data write access. As a result it is possible to transfer dissimilar data from the processors into the bridge in a combined (lockstep comparison) mode. In a subsequent phase the bridge control mechanism responds to a read destination address supplied in common by the first and second processing sets for a dissimilar data read access to supply data read from a determined one of the dissimilar data registers to the first and second processing sets. In this manner the data from one processing set can be copied to the other processing set while in a combined mode.