公开(公告)号：US20250017008A1

公开(公告)日：2025-01-09

申请号：US18439835

申请日：2024-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang Lib KIM ,  Sungsu MOON ,  Sea Hoon LEE ,  Junhee LIM ,  Seongpil CHANG

IPC: H10B43/27 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes a cell array region and a connection region. A gate stacking structure includes gate electrodes and interlayer insulation layers that are alternately stacked. The gate stacking structure extends in a first direction and is separated by separation structures in a second direction. A channel structure penetrates the gate stacking structure in the cell array region. Gate contact portions penetrate the gate stacking structure in the connection region. The gate contact portions are electrically connected to the gate electrodes, respectively. An insulation layer is provided separately from the separation structure and covers at least the gate stacking structure. The insulation layer comprises a base insulation portion and a hydrogen-containing insulation portion. The hydrogen-containing insulation portion includes a hydrogen-containing portion having a different material from a material of the base insulation portion. The hydrogen-containing portion including hydrogen.

公开(公告)号：US20240179899A1

公开(公告)日：2024-05-30

申请号：US18514158

申请日：2023-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseon KIM ,  Nakjin SON ,  Dongjin LEE ,  Junhee LIM ,  Seongsu KIM ,  Hanmin CHO ,  Chiwoong HAM

IPC: H10B41/41 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/41 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A NAND flash device may include a peripheral circuit including a transistor, a substrate, and a device isolation region defining an active region of the substrate. The transistor may include a first gate structure on the active region. The transistor may include source and drain regions extending in a first direction in the active region on both sides of the first gate structure, which may include a first lightly-doped source and drain region adjacent to the first gate structure and a second lightly-doped source and drain region integrally connected thereto. The second lightly-doped source and drain region may be arranged farther from the first gate structure than the first lightly-doped source and drain region. The second lightly-doped source and drain region may have a smaller width in the second direction than a width of the first lightly-doped source and drain region in the second direction.

公开(公告)号：US20220406808A1

公开(公告)日：2022-12-22

申请号：US17724002

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Junhee LIM ,  Hakseon KIM ,  Nakjin SON ,  Jeongeun KIM ,  Juseong MIN ,  Changheon LEE

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: A semiconductor device includes a lower level layer including a peripheral circuit; and an upper level layer provided on the lower level layer, the upper level layer including a vertically-extended memory cell string, wherein the lower level layer includes a first substrate; a device isolation layer defining a first active region of the first substrate; and a first gate structure including a first gate insulating pattern, a first conductive pattern, a first metal pattern, and a first capping pattern, which are sequentially stacked on the first active region, wherein the first conductive pattern comprises a doped semiconductor material, and the device isolation layer covers a first side surface of the first conductive pattern, and the first metal pattern includes a first body portion on the first conductive pattern.

公开(公告)号：US20210134884A1

公开(公告)日：2021-05-06

申请号：US17088168

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho LEE ,  Gwanhyeob KOH ,  Ilmok PARK ,  Junhee LIM

IPC: H01L27/24 ,  H01L27/1157 ,  G11C11/16 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/22 ,  H01L27/11575 ,  G11C14/00 ,  G11C5/02 ,  G11C16/04

Abstract: Disclosed is a semiconductor device including first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.

公开(公告)号：US20190267046A1

公开(公告)日：2019-08-29

申请号：US16411106

申请日：2019-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho LEE ,  Gwanhyeob KOH ,  Junhee LIM ,  Hongsoo KIM ,  Chang-hoon JEON

IPC: G11C5/06 ,  H01L27/11573 ,  H01L27/22 ,  H01L27/1157 ,  H01L43/10 ,  G11C13/00 ,  H01L25/18 ,  G11C11/16 ,  G11C16/04

Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.

公开(公告)号：US20180358555A1

公开(公告)日：2018-12-13

申请号：US16010447

申请日：2018-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： KILHO LEE ,  GWANHYEOB KOH ,  ILMOK PARK ,  Junhee LIM

IPC: H01L45/00 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16 ,  G11C13/00 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/1157

CPC classification number: H01L45/1233 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C13/0004 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144

Abstract: Disclosed is a semiconductor device including first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.