公开(公告)号：US20240324194A1

公开(公告)日：2024-09-26

申请号：US18602778

申请日：2024-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjin LEE ,  Junhee LIM ,  Hakseon KIM ,  Kangoh YUN ,  Sohyun LEE

IPC: H10B41/35 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B80/00

CPC classification number: H10B41/35 ,  G11C16/0483 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B80/00 ,  H01L2225/06506

Abstract: An integrated circuit device includes a substrate including an active region including a central active region, base active regions and extended active regions integrated together and defined by a device isolation film. A drain region is located in the central active region, and source regions are respectively located in the base active regions. The base active regions are spaced apart from each other in different diagonal directions with respect to the central active region in a plan view. The extended active regions each have an L-shape, connect the central active region and the base active regions, and are spaced apart from each other. Gate structures that respectively cross the base active regions and are spaced apart from each other on the substrate. The central active region, the extended active regions, the base active regions, and the gate structures configure pass transistors, and the pass transistors share the drain region.

公开(公告)号：US20240431113A1

公开(公告)日：2024-12-26

申请号：US18529241

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang Lib KIM ,  Sea Hoon LEE ,  Junhee LIM

IPC: H10B43/40 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes a circuit region including a peripheral circuit on a substrate; and a cell region adjacent to the circuit region. The cell region includes a cell array region and a connecting region. The cell region also includes a gate stack that includes an interlayer insulating layer and a gate electrode, alternately stacked on the substrate; a channel in the cell array region that extends through the gate stack; a main support in the connecting region that extends through the gate stack; and a contact electrode in the connecting region connected to the gate electrode through the gate stack. The main support includes a first portion extending along a first direction; and a second portion extending from the first portion in a second direction crossing the first direction. At least a portion of the contact electrode is surrounded by the first and second portions of the main support.

公开(公告)号：US20230389322A1

公开(公告)日：2023-11-30

申请号：US18133278

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjin LEE ,  Junhee LIM ,  Donghoon KWON ,  Hakseon KIM ,  Nakjin SON ,  Yanghee LEE ,  Juhyun LEE

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device includes a peripheral circuit region including a first substrate, circuit elements on the first substrate, a first interconnection structure electrically connected to the circuit elements, first to fourth peripheral region insulating layer; and a memory cell region including a second substrate on the peripheral circuit region and having a first region and a second region, gate electrodes stacked on the first region, a cell region insulating layer covering the gate electrodes, channel structures passing through the gate electrodes, and a second interconnection structure electrically connected to the gate electrodes and the channel structures. The peripheral circuit region further includes first to fourth lower protective layers, at least one of the first, second, third and fourth lower protective layers includes a hydrogen diffusion barrier layer configured to inhibit a hydrogen element included in the cell region insulating layer from diffusing to the circuit elements, and including aluminum oxide.

公开(公告)号：US20210028283A1

公开(公告)日：2021-01-28

申请号：US16822389

申请日：2020-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkweon BAEK ,  Taeyoung KIM ,  Hakseon KIM ,  Kangoh YUN ,  Changhoon JEON ,  Junhee LIM

IPC: H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes a gate structure disposed on a substrate. The gate structure has a first sidewall and a second sidewall facing the first sidewall. A first impurity region is disposed within an upper portion of the substrate. The first impurity region is spaced apart from the first sidewall. A third impurity region is within the upper portion of the substrate. The third impurity region is spaced apart from the second sidewall. A first trench is disposed within the substrate between the first sidewall and the first impurity region. The first trench is spaced apart from the first sidewall. A first barrier insulation pattern is disposed within the first trench.

公开(公告)号：US20180358056A1

公开(公告)日：2018-12-13

申请号：US15854551

申请日：2017-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho LEE ,  Gwanhyeob KOH ,  Junhee LIM ,  Hongsoo KIM ,  Chang-hoon JEON

IPC: G11C5/06 ,  G11C16/04 ,  G11C11/16 ,  H01L25/18 ,  H01L27/1157 ,  H01L27/22 ,  H01L27/11573 ,  H01L43/10

CPC classification number: G11C5/06 ,  G11C11/005 ,  G11C11/161 ,  G11C13/0002 ,  G11C13/0004 ,  G11C16/0483 ,  G11C2213/72 ,  G11C2213/76 ,  H01L25/18 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/222 ,  H01L43/10

Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.

公开(公告)号：US20250078929A1

公开(公告)日：2025-03-06

申请号：US18679809

申请日：2024-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kibong MOON ,  Suck-Soo KIM ,  Tae Hun KIM ,  Hyoje BANG ,  Seung Jae BAIK ,  Sung-Bok LEE ,  Jaeduk LEE ,  Junhee LIM

IPC: G11C16/04 ,  G11C5/06 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device may include a substrate, a plurality of cell strings perpendicular to an upper surface of the substrate, and a bit line connected to at least six of the cell strings. Each of the cell strings may include a plurality of memory cells connected in series to each other in a direction perpendicular to the upper surface of the substrate, first to fourth ground selection transistors connected in series to each other between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and the bit line. A first one of the first to fourth selection ground selection transistors may have a first threshold voltage distribution, and a second one of the first to fourth ground selection transistors may have a second threshold voltage distribution. The second threshold voltage distribution may be different from the first threshold voltage distribution.

公开(公告)号：US20240324201A1

公开(公告)日：2024-09-26

申请号：US18441645

申请日：2024-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang Lib KIM ,  Seahoon LEE ,  Junhee LIM

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A semiconductor memory device includes a substrate, a plurality of gate stack structures on the substrate that include a plurality of gate lines stacked and a plurality of insulating films between the plurality of gate lines, a plurality of first separation insulating films that are alternately stacked with the plurality of gate lines, where the plurality of gate stack structures and the plurality of first separation insulating films define a contact hole, a contact electrode that is in the contact hole and contacts the plurality of gate stack structures, and one or more second separation insulating film that is on an uppermost gate line of one or more of the plurality of gate stack structures and separates the contact electrode from the uppermost gate line.

公开(公告)号：US20240206182A1

公开(公告)日：2024-06-20

申请号：US18523033

申请日：2023-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changmin CHOI ,  Ryoongbin LEE ,  Dongjin LEE ,  Junhee LIM

IPC: H10B43/40 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10

CPC classification number: H10B43/40 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10

Abstract: A non-volatile memory device including a memory cell array including a plurality of word lines stacked on a substrate in a first direction perpendicular to an upper surface of the substrate, and a common source line below the plurality of word lines, a plurality, of driving signal lines connected to a row decoder, and a plurality of pass transistor arrays each including a plurality of vertical pass transistors respectively connected the plurality of driving signal lines and the plurality of word lines, wherein each of the plurality of pass transistor arrays further include an active region including a drain to which at least two of the plurality of vertical pass transistors are simultaneously bonded, and a main contact applying a signal to the active region.

公开(公告)号：US20230049653A1

公开(公告)日：2023-02-16

申请号：US17722672

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Dongsoo WOO ,  Junhee LIM

IPC: H01L23/535 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device including a substrate including a cell array region and a connection region, an electrode structure stacked on the substrate, each of the electrodes including a line portion on the cell array region and a pad portion on the connection region, Vertical patterns penetrating the electrode structure, a cell contact on the connection region and connected to the pad portion, an insulating pillar below the cell contact, with the pad portion interposed therebetween may be provided. The pad portion may include a first portion having a top surface higher than the line portion, and a second portion including a first protruding portion, the first protruding portion extending from the first portion toward the substrate and covering a top surface of the insulating pillar.

公开(公告)号：US20190341456A1

公开(公告)日：2019-11-07

申请号：US16515412

申请日：2019-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moorym CHOI ,  Bongyong LEE ,  Junhee LIM

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device includes common source regions, an electrode structure between the common source regions, first channel structures penetrating the electrode structure, and second channel structures between the first channel structures and penetrating the electrode structures. The electrode structure includes electrodes vertically stacked on a substrate. The first channel structures include a first semiconductor pattern and a first vertical insulation layer. The second channel structures include a second vertical insulation layer surrounding a second semiconductor pattern. The second vertical insulation layer has a bottom surface lower than a bottom surface of the first vertical insulation layer.