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公开(公告)号：US20230247340A1
公开(公告)日：2023-08-03
申请号：US18102426
申请日：2023-01-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan LEE
IPC: H04R1/10
CPC classification number: H04R1/1016 , H04R2460/11
Abstract: An example earphone includes a housing having a speaker module embedded therein and an ear tip connected to the housing. The housing includes a coupling portion having a sound hole formed in an end portion thereof. The ear tip includes a first tip including a first hollow aligned with the sound hole in a first direction and a first sidewall that surrounds the first hollow and a second tip including a second hollow in which the first tip is accommodated and a second sidewall that surrounds the second hollow, the first direction being a direction toward the speaker module from the sound hole. The first tip includes a first connecting portion having a protrusion form on an end portion thereof in the first direction. The coupling portion includes, on one surface thereof, a second connecting portion including a groove with which the first connecting portion is engaged. A connection gap is formed between facing surfaces of the first connecting portion and the second connecting portion, and the coupling portion of the housing and the ear tip are connected so as to be rotatable relative to each other.
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公开(公告)号：US20230024307A1
公开(公告)日：2023-01-26
申请号：US17590087
申请日：2022-02-01
Applicant: Samsung Electronics Co., Ltd
Inventor： Kyunghwan LEE , Yongseok KIM , Hyuncheol KIM , Jongman PARK , Dongsoo WOO
IPC: H01L27/11507
Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a substrate; a transistor disposed above the substrate, the transistor having a channel region defining an inner space; and a capacitor passing through the transistor in a vertical direction in the inner space.
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公开(公告)号：US20220367479A1
公开(公告)日：2022-11-17
申请号：US17716215
申请日：2022-04-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghwan LEE , Yongseok KIM , Hyuncheol KIM , Dongsoo WOO , Sungwon YOO
IPC: H01L27/108 , H01L29/423 , H01L29/792
Abstract: A semiconductor memory device includes a semiconductor substrate a gate structure extending in a vertical direction on the semiconductor device, a plurality of charge trap layers spaced apart from each other in the vertical direction and each having a horizontal cross-section with a first ring shape surrounding the gate structure, a plurality of semiconductor patterns spaced apart from each other in the vertical direction and each having a horizontal cross-section with a second ring shape surrounding the plurality of charge trap layers, a source region and a source line at one end of each of the plurality of semiconductor patterns in a horizontal direction, and a drain region and a drain line at an other end of each of the plurality of semiconductor patterns in the horizontal direction. The gate structure may include a gate insulation layer and a gate electrode layer.
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公开(公告)号：US20220352170A1
公开(公告)日：2022-11-03
申请号：US17725069
申请日：2022-04-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan LEE , Yongseok KIM , Ilgweon KIM , Hyeoungwon SEO , Sungwon YOO , Jaeho HONG
IPC: H01L27/108
Abstract: A semiconductor memory device includes a word line extending in a vertical direction, a semiconductor pattern having a ring-shaped horizontal cross-section that extends around the word line, a bit line disposed at a first end of the semiconductor pattern, and a capacitor structure disposed at second end of the semiconductor pattern. The capacitor structure includes a lower electrode layer electrically connected to the second end of the semiconductor pattern, having a ring-shaped horizontal cross-section, and including a connector extending in the vertical direction. A first segment extends in a horizontal direction from an upper end of the connector, and a second segment extends in the horizontal direction from a lower end of the connector. An upper electrode layer surrounded by the lower electrode layer, extends in the vertical direction, and a capacitor dielectric layer is between the lower electrode layer and the upper electrode layer.
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公开(公告)号：US20220216239A1
公开(公告)日：2022-07-07
申请号：US17503713
申请日：2021-10-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungwon YOO , Yongseok KIM , Ilgweon KIM , Hyuncheol KIM , Hyeoungwon SEO , Kyunghwan LEE , Jaeho HONG
IPC: H01L27/12 , H01L27/13 , H01L25/065 , H01L25/18 , H01L21/84
Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a data storage layer including data storage devices, an interconnection layer disposed on the data storage layer, and a selection element layer provided between the data storage layer and the interconnection layer. The interconnection layer may include bit lines extending in a first direction. The selection element layer may include a cell transistor connected between one of the data storage devices and one of the bit lines, and the cell transistor may include an active pattern and a word line, which crosses the active pattern and is extended in a second direction crossing the first direction.
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Patent Agency Ranking
16.发明申请公开(公告)号：US20250156480A1
公开(公告)日：2025-05-15
申请号：US19024992
申请日：2025-01-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Soohyung KIM , Sejeong KWON , Yul KIM , Jungho PARK , Wonsuk YANG , Kyunghwan LEE , Junhyuk LEE
IPC: G06F16/901 , G06F11/34 , G06F18/214 , G06F18/2321
Abstract: A control method for an electronic apparatus includes, obtaining, based on log data of devices, a first graph including first information regarding devices and second information regarding relevance among the devices; obtaining an edge-based second graph based on the first graph such that edges of the second graph include edges of the first graph, and the second edges include third information regarding clustering rules from the edges of the first graph; converting the second graph into a node-based third graph such that nodes of the third graph include the third information; converting the third information into probability labels of the nodes, wherein a probability label indicates relevance between two devices from among the devices; converting the third graph into an edge-based fourth graph such that edges of the fourth graph include the probability labels; and clustering the devices into groups based on the first graph and the fourth graph.
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公开(公告)号：US20250149908A1
公开(公告)日：2025-05-08
申请号：US19012232
申请日：2025-01-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sangwoo KANG , Kyunghwan LEE
Abstract: An electronic device according to one embodiment may comprise a first battery, a second battery, a first charging circuit configured to provide power of a first voltage to the first battery, a second charging circuit configured to provide power of a second voltage to the second battery, a first limiter disposed between the first battery and the second charging circuit, and a processor. The processor according to one embodiment can be configured to identify the first voltage to be applied to the first battery, request, on the basis of the first voltage, from an external power source, power of an input voltage corresponding to twice the first voltage, control, on the basis that the input voltage corresponding to twice the first voltage provided from the external power source is applied to the first charging circuit, the first charging circuit such that power of the first voltage is supplied to the first battery, and control, on the basis that the input voltage corresponding to twice the first voltage provided from the external power source is applied to the second charging circuit, the second charging circuit such that power of the second voltage is supplied to the second battery.
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公开(公告)号：US20250142806A1
公开(公告)日：2025-05-01
申请号：US19003119
申请日：2024-12-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan LEE , Yongseok KIM , Ilgweon KIM , Hyeoungwon SEO , Sungwon YOO , Jaeho HONG
IPC: H10B12/00
Abstract: A semiconductor memory device includes a word line extending in a vertical direction, a semiconductor pattern having a ring-shaped horizontal cross-section that extends around the word line, a bit line at a first end of the semiconductor pattern, and a capacitor structure at second end of the semiconductor pattern. The capacitor structure includes a lower electrode layer electrically connected to the second end of the semiconductor pattern, having a ring-shaped horizontal cross-section, and including a connector extending in the vertical direction. A first segment extends in a horizontal direction from an upper end of the connector, and a second segment extends in the horizontal direction from a lower end of the connector. An upper electrode layer surrounded by the lower electrode layer, extends in the vertical direction, and a capacitor dielectric layer is between the lower electrode layer and the upper electrode layer.
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公开(公告)号：US20240170072A1
公开(公告)日：2024-05-23
申请号：US18510074
申请日：2023-11-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Suhwan LIM , Kyunghwan LEE , Yongseok KIM
CPC classification number: G11C16/16 , G11C16/0433 , G11C16/24 , G11C16/32
Abstract: A storage device capable of performing erase operations in units smaller than blocks may include nonvolatile memory, and processing circuitry configured to, apply an erase voltage to a first bit line of the plurality of bit lines of at least one memory block of the plurality of memory blocks, apply an erase prohibition voltage to a second bit line of the plurality of bit lines, the erase prohibition voltage having a voltage level lower than a voltage level of the erase voltage, and float the common source line to cause an erasure of data stored in at least one first memory cell included in at least one first cell string connected to the first bit line by floating the common source line, and preserve data stored in at least one second memory cell included in at least one second cell string connected to the second bit line.
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公开(公告)号：US20230420993A1
公开(公告)日：2023-12-28
申请号：US18343511
申请日：2023-06-28
Inventor： Kyunghwan LEE , Jungik HA , Geonhong MIN , Junhyeong LEE
CPC classification number: H02J50/12 , H02J2207/20 , H02J7/0047 , H02J7/00712
Abstract: According to an embodiment, an electronic device for wirelessly receiving power may include: a power reception circuit including a coil, an impedance compensation circuit electrically connected to the power reception circuit, a rectifier circuit electrically connected to the impedance compensation circuit, a battery electrically connected to the rectifier circuit, and a control circuit electrically and/or operatively connected to the impedance compensation circuit, the rectifier circuit, and the battery. According to an embodiment, the control circuit may be configured to: rectify, by controlling the rectifier circuit, power received wirelessly from an external electronic device through the power reception circuit and the impedance compensation circuit into direct current (DC) power. According to an embodiment, the control circuit may be configured to identify at least one of a voltage or a current of the rectified DC power. According to an embodiment, the control circuit may be configured to determine a duty cycle of a control signal to control the impedance compensation circuit, based on the at least one of the voltage or the current. According to an embodiment, the control circuit may be configured to adjust a first voltage output by the impedance compensation circuit by controlling the impedance compensation circuit based on the duty cycle. According to an embodiment, impedance of the power reception circuit may be compensated based on the adjusted first voltage of the impedance compensation circuit.
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