公开(公告)号：US20230344250A1

公开(公告)日：2023-10-26

申请号：US18218168

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Yeongil KIM

IPC: H02J7/00 ,  G06F1/26 ,  H02M3/158

CPC classification number: H02J7/00308 ,  G06F1/266 ,  H02M3/158

Abstract: According to certain embodiments, an electronic device comprises: a battery; an interface module; a detection module electrically connected with the interface module, the detection module configured to detect than an external electronic device for receiving power is connected to the interface module; a protection module electrically connected with the interface module and comprising a first switching element; and a charging module electrically connected with the protection module, the detection module, and the battery, and comprising a voltage conversion circuit and a second switching element, the charging module configured to provide a first power to the protection module when the detection module detects connection of the external electronic device, wherein the first switching element is configured to turn on after receiving the first power, wherein the charging module is configured to raise a power from the battery to a designated value through the voltage conversion circuit, thereby resulting in a second power, and, when a designated first time is elapsed after the power from the battery is raised to the designated value, turn on the second switching element, thereby providing the second power to the protection module.

公开(公告)号：US20230247103A1

公开(公告)日：2023-08-03

申请号：US18300066

申请日：2023-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungho PARK ,  Yul KIM ,  Sejeong KWON ,  Soohyung KIM ,  Wonsuk YANG ,  Kyunghwan LEE ,  Junhyuk LEE

IPC: H04L67/50 ,  H04L43/04 ,  H04L41/16

CPC classification number: H04L67/535 ,  H04L43/04 ,  H04L41/16

Abstract: An electronic apparatus is provided. The electronic apparatus includes a communication interface, a memory storing log data with respect to external devices connected to the electronic apparatus, and a processor configured to identify a plurality of external devices having a history of being connected to the same internet protocol (IP) based on the log data, acquire, based on the log data, a first feature vector with respect to a relationship between the plurality of external devices and a second feature vector with respect to each of the plurality of external devices, acquire a graph of the relationship between the plurality of external devices based on the first feature vector and the second feature vector, and define at least one group configured by the plurality of external devices based on the graph.

公开(公告)号：US20230112067A1

公开(公告)日：2023-04-13

申请号：US17880083

申请日：2022-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan LEE ,  Youngdeog KOH ,  Kwangjoo KIM ,  Jinju KIM ,  Jihwan CHUN

IPC: A47B96/20 ,  C25D11/18

Abstract: A decoration panel for home appliances having excellent reflectivity and durability, the decoration panel being applicable to outer sides of various home appliances, a home appliance including the decoration panel, and a method for manufacturing the decoration panel. More specifically, the decoration panel for home appliances includes: an aluminum substrate with one surface in which an engraved pattern having a preset width and a preset depth is formed, the engraved pattern having micro unevenness formed in a surface of the engraved pattern; a porous aluminum oxide layer formed on the engraved pattern; and a sealing layer formed to close a plurality of pores of the porous aluminum oxide layer, wherein an edge of the aluminum substrate is in a Chamfering (C) shape or a Rounding (R) shape.

公开(公告)号：US20230049653A1

公开(公告)日：2023-02-16

申请号：US17722672

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Dongsoo WOO ,  Junhee LIM

IPC: H01L23/535 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device including a substrate including a cell array region and a connection region, an electrode structure stacked on the substrate, each of the electrodes including a line portion on the cell array region and a pad portion on the connection region, Vertical patterns penetrating the electrode structure, a cell contact on the connection region and connected to the pad portion, an insulating pillar below the cell contact, with the pad portion interposed therebetween may be provided. The pad portion may include a first portion having a top surface higher than the line portion, and a second portion including a first protruding portion, the first protruding portion extending from the first portion toward the substrate and covering a top surface of the insulating pillar.

公开(公告)号：US20220029095A1

公开(公告)日：2022-01-27

申请号：US17192093

申请日：2021-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Hyeoungwon SEO ,  Sungwon YOO ,  Kyunghwan LEE ,  Jaeho HONG

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/00

Abstract: A vertical variable resistance memory device including gate electrodes spaced apart from each other in a first direction on a substrate, each of the gate electrodes including graphene and extending in a second direction, the first direction being substantially perpendicular to an upper surface of the substrate and the second direction being substantially parallel to the upper surface of the substrate; first insulation patterns between the gate electrodes, each of the first insulation patterns including boron nitride (BN); and at least one pillar structure extending in the first direction through the gate electrodes and the first insulation patterns on the substrate, wherein the at least one pillar structure includes a vertical gate electrode extending in the first direction; and a variable resistance pattern on a sidewall of the vertical gate electrode.

公开(公告)号：US20250132589A1

公开(公告)日：2025-04-24

申请号：US19007551

申请日：2025-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwoo KANG ,  Kyunghwan LEE

IPC: H02J7/00

Abstract: An electronic device according to various embodiments of the disclosure may include a first charging circuit connected to a first node and a second node, a second charging circuit connected to the first node and a third node, a switch connected to the second node and the third node, a battery connected to the second node, a system circuit connected to the third node, and a processor. In addition, various embodiments may be possible.

公开(公告)号：US20240422964A1

公开(公告)日：2024-12-19

申请号：US18421187

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Wonsok LEE ,  Juho LEE ,  Daewon HA

IPC: H10B12/00 ,  H01L29/10

Abstract: A semiconductor memory device includes a memory cell array having a three-dimensional structure, the memory cell array including a plurality of memory cells repeatedly arranged in a first lateral direction, a second lateral direction, and a vertical direction, wherein the first lateral direction and the second lateral direction are perpendicular to each other, and the vertical direction is perpendicular to each of the first lateral direction and the second lateral direction, wherein each of the plurality of memory cells includes two transistors including at a least portions of two word lines passing through the memory cell in the vertical direction and at least portions of two bit lines respectively on both sides of the two word lines in the first lateral direction, each of the two bit line extending along the second lateral direction, and each of the plurality of memory cells does not include a capacitor.

公开(公告)号：US20240266287A1

公开(公告)日：2024-08-08

申请号：US18457907

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Daewon HA

IPC: H01L23/528 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10 ,  H10B51/20

CPC classification number: H01L23/5283 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/20

Abstract: A semiconductor device may include first conductive lines spaced apart from each other in a first direction on a substrate, second conductive lines spaced apart from the first conductive lines in a second direction, a gate electrode between the first and second conductive lines and extending in the first direction, a first selection gate electrode between the first conductive lines and the gate electrode and extending in the first direction, a plurality of channel patterns surrounding a side surface of the gate electrode and spaced apart from each other in the first direction, a plurality of first selection channel patterns surrounding a side surface of the first selection gate electrode and a ferroelectric pattern between the gate electrode and each of the channel patterns. The first selection channel patterns may be spaced apart from each other in the first direction and connected to the channel patterns, respectively.

公开(公告)号：US20240164108A1

公开(公告)日：2024-05-16

申请号：US18235000

申请日：2023-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Daewon HA

IPC: H10B51/20 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10

Abstract: A three-dimensional ferroelectric memory device includes a channel on a substrate and extending in a vertical direction substantially perpendicular to an upper surface of the substrate, a gate insulation pattern and a conductive pattern stacked on and surrounding a sidewall of the channel in a horizontal direction substantially parallel to the upper surface of the substrate, a ferroelectric pattern contacting a portion of an outer sidewall of the conductive pattern, a gate electrode contacting the ferroelectric pattern, and first and second source/drain patterns contacting lower and upper surfaces, respectively, of the channel.

公开(公告)号：US20230307448A1

公开(公告)日：2023-09-28

申请号：US17950434

申请日：2022-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Sungil PARK ,  Jae Hyun PARK ,  Daewon HA

IPC: H01L27/06 ,  H01L21/822 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/785

Abstract: A three-dimensional semiconductor device comprises a first active region on a substrate and including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern, a second active region stacked on the first active region and including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, a gate electrode on the lower channel pattern and the upper channel pattern, a first active contact electrically connected to the lower source/drain pattern, an upper separation structure between the first active contact and the upper source/drain pattern, a second active contact electrically connected to the upper source/drain pattern, and a lower separation structure between the second active contact and the lower source/drain pattern.