公开(公告)号：US20240429057A1

公开(公告)日：2024-12-26

申请号：US18823864

申请日：2024-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGMIN KIM ,  DAEWON HA

IPC: H01L21/306 ,  H01L21/20 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/84

Abstract: Methods of forming a semiconductor device and semiconductor device formed by the methods are provided. The methods of forming a semiconductor device may include providing a first substrate and a first bonding layer that is provided on the first substrate, forming a sacrificial pattern and an active pattern on a second substrate, forming a second bonding layer on the active pattern, bonding the second bonding layer onto the first bonding layer, removing the second substrate, and removing the sacrificial pattern to expose the active pattern. Forming the sacrificial pattern and the active pattern on the second substrate may include forming a preliminary sacrificial pattern and the active pattern on the second substrate and oxidizing the preliminary sacrificial pattern. The preliminary sacrificial pattern and the active pattern may be sequentially stacked on the second substrate.

公开(公告)号：US20240413158A1

公开(公告)日：2024-12-12

申请号：US18809922

申请日：2024-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGMIN KIM ,  DAEWON HA

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

Abstract: A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.

公开(公告)号：US20240339516A1

公开(公告)日：2024-10-10

申请号：US18491550

申请日：2023-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGMIN KIM

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L21/28123 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775

Abstract: A semiconductor device may include: a substrate; a lower pattern extending from the substrate in a first direction; a channel pattern disposed on the lower pattern; a source/drain pattern disposed on sides of the channel pattern; a first gate structure and a second gate structure extending in a second direction intersecting the first direction and surrounding respective portions of the channel pattern; and a separation structure disposed between the first gate structure and the second gate structure, and including a first portion extending in the first direction and a second portion protruding from the first portion toward the channel pattern, wherein the first gate structure includes first and second conductive patterns stacked sequentially from the respective portion of the channel pattern, and a length of the second conductive pattern in the second direction is equal to or greater than a length of the second portion in the second direction.

公开(公告)号：US20230402460A1

公开(公告)日：2023-12-14

申请号：US18239241

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGMIN KIM ,  Daewon Ha

IPC: H01L27/092 ,  H01L29/08 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L23/522

CPC classification number: H01L27/0924 ,  H01L29/0847 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42356 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823814 ,  H01L23/5226 ,  H01L21/02636

Abstract: A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.

公开(公告)号：US20230197858A1

公开(公告)日：2023-06-22

申请号：US18110961

申请日：2023-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOONMOON JUNG ,  DAEWON HA ,  SUNGMIN KIM ,  HYOJIN KIM ,  KEUN HWI CHO

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78645 ,  H01L29/6675 ,  H01L29/7827 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/78696

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

公开(公告)号：US20220328485A1

公开(公告)日：2022-10-13

申请号：US17851155

申请日：2022-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： DEOKHAN BAE ,  SUNGMIN KIM ,  JUHUN PARK ,  YURI LEE ,  YOONYOUNG JUNG ,  SOOYEON HONG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuit devices may include a fin-type active region, a gate line extending on the fin-type active region, a source/drain region on the fin-type active region and adjacent to the gate line, an interlayer insulating film covering the source/drain region, a source/drain contact hole penetrating the interlayer insulating film toward the source/drain region, a metal plug in the source/drain contact hole, and a conductive barrier film covering a sidewall of the metal plug in the source/drain contact hole. The metal plug includes a lateral expansion portion and a through portion vertically extending from the lateral expansion portion toward the source/drain region. A width of the lateral expansion is greater than a width of the through portion, and a topmost surface of the conductive barrier film is closer than a topmost surface of the metal plug to the substrate.

公开(公告)号：US20220216207A1

公开(公告)日：2022-07-07

申请号：US17700590

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： DEOKHAN BAE ,  SUNGMIN KIM ,  JUHUN PARK ,  YURI LEE ,  YOONYOUNG JUNG ,  SOOYEON HONG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

公开(公告)号：US20220173103A1

公开(公告)日：2022-06-02

申请号：US17675163

申请日：2022-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGMIN KIM ,  DAEWON HA

IPC: H01L27/092 ,  H01L29/08 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L23/522

Abstract: A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.

公开(公告)号：US20210384295A1

公开(公告)日：2021-12-09

申请号：US17101703

申请日：2020-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUHUN PARK ,  DEOKHAN BAE ,  SUNGMIN KIM ,  YURI LEE ,  YOONYOUNG JUNG ,  SOOYEON HONG

IPC: H01L29/06 ,  H01L27/092 ,  H03K19/0185

Abstract: A semiconductor device includes a substrate having PMOSFET and NMOSFET regions spaced apart from each other in a direction, a device isolation layer provided on the substrate that defines first and second active patterns respectively on the PMOSFET and NMOSFET regions, a gate electrode crossing the first and second active patterns, first and second source/drain patterns respectively provided on the first and second active patterns respectively and near the gate electrode, and an active contact extending in the direction and coupled to the first and second source/drain patterns. The active contact includes first and second body portions, which are respectively provided on the first and the second source/drain patterns, and a first protruding portion and a recessed portion, which are provided between the first and second body portions and on the device isolation layer between the PMOSFET and NMOSFET regions. The recessed portion has an upwardly recessed bottom.

公开(公告)号：US20200373301A1

公开(公告)日：2020-11-26

申请号：US16870135

申请日：2020-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGMIN KIM ,  DAEWON HA

IPC: H01L27/092 ,  H01L29/08 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L23/522 ,  H01L21/8238

Abstract: A semiconductor device includes an arrive pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connoted to the first source/drain pattern.