公开(公告)号：US20210391433A1

公开(公告)日：2021-12-16

申请号：US17313638

申请日：2021-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGMIN KIM ,  JUHUN PARK ,  DEOKHAN BAE ,  MYUNGYOON UM ,  YURI LEE ,  INYEAL LEE ,  YOONYOUNG JUNG ,  SOOYEON HONG

IPC: H01L29/417 ,  H01L27/092

Abstract: A semiconductor device includes a first active (e.g., PMOSFET) region and an adjacent second active (e.g., NMOSFET) region on a substrate, a device isolation layer on the substrate and defining a first active pattern on the first active region and a second active pattern on the second active region, a gate electrode crossing the first and second active patterns, a first source/drain pattern and a second source/drain pattern adjacent to a side of the gate electrode, an interlayer insulating layer on the gate electrode, a first active contact penetrating the interlayer insulating layer to connect the first source/drain pattern and a second active contact penetrating the interlayer insulating layer to connect the second source/drain pattern and a buffer layer provided in an upper region of the interlayer insulating layer and interposed between the first active contact and the second active contact, wherein the buffer layer includes a material having etch selectivity with respect to the interlayer insulating layer.

公开(公告)号：US20230063607A1

公开(公告)日：2023-03-02

申请号：US17689721

申请日：2022-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DEOKHAN BAE ,  JUHUN PARK ,  YURI LEE ,  YOONYOUNG JUNG ,  SOOYEON HONG

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

Abstract: A semiconductor device includes first to fourth gate structures sequentially disposed in a first horizontal direction. Each of the first to fourth gate structures includes a gate electrode and a gate capping layer and first to third source/drain regions disposed among the first to fourth gate structures. A first narrow source/drain contact, a first wide source/drain contact, and a second narrow source/drain contact are disposed among the first to fourth gate structures and contact the first to third source/drain regions, respectively. The first to fourth gate structures are disposed with first to third distances there among. The second distance is greater than the first distance and the third distance. A lower end of the first narrow source/drain contact is disposed at a higher level than a lower end of the first wide source/drain contact.

公开(公告)号：US20220328485A1

公开(公告)日：2022-10-13

申请号：US17851155

申请日：2022-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： DEOKHAN BAE ,  SUNGMIN KIM ,  JUHUN PARK ,  YURI LEE ,  YOONYOUNG JUNG ,  SOOYEON HONG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuit devices may include a fin-type active region, a gate line extending on the fin-type active region, a source/drain region on the fin-type active region and adjacent to the gate line, an interlayer insulating film covering the source/drain region, a source/drain contact hole penetrating the interlayer insulating film toward the source/drain region, a metal plug in the source/drain contact hole, and a conductive barrier film covering a sidewall of the metal plug in the source/drain contact hole. The metal plug includes a lateral expansion portion and a through portion vertically extending from the lateral expansion portion toward the source/drain region. A width of the lateral expansion is greater than a width of the through portion, and a topmost surface of the conductive barrier film is closer than a topmost surface of the metal plug to the substrate.

公开(公告)号：US20220216207A1

公开(公告)日：2022-07-07

申请号：US17700590

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： DEOKHAN BAE ,  SUNGMIN KIM ,  JUHUN PARK ,  YURI LEE ,  YOONYOUNG JUNG ,  SOOYEON HONG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

公开(公告)号：US20210384295A1

公开(公告)日：2021-12-09

申请号：US17101703

申请日：2020-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUHUN PARK ,  DEOKHAN BAE ,  SUNGMIN KIM ,  YURI LEE ,  YOONYOUNG JUNG ,  SOOYEON HONG

IPC: H01L29/06 ,  H01L27/092 ,  H03K19/0185

Abstract: A semiconductor device includes a substrate having PMOSFET and NMOSFET regions spaced apart from each other in a direction, a device isolation layer provided on the substrate that defines first and second active patterns respectively on the PMOSFET and NMOSFET regions, a gate electrode crossing the first and second active patterns, first and second source/drain patterns respectively provided on the first and second active patterns respectively and near the gate electrode, and an active contact extending in the direction and coupled to the first and second source/drain patterns. The active contact includes first and second body portions, which are respectively provided on the first and the second source/drain patterns, and a first protruding portion and a recessed portion, which are provided between the first and second body portions and on the device isolation layer between the PMOSFET and NMOSFET regions. The recessed portion has an upwardly recessed bottom.