公开(公告)号：US11282787B2

公开(公告)日：2022-03-22

申请号：US16879009

申请日：2020-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L29/40 ,  H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L29/06 ,  G11C5/10 ,  H01L29/423 ,  H01L27/108 ,  H01L21/768

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US09761591B2

公开(公告)日：2017-09-12

申请号：US15148405

申请日：2016-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Sohyun Park ,  Bong-Soo Kim ,  Yoosang Hwang ,  Dong-Wan Kim ,  Junghoon Han

IPC: H01L21/20 ,  H01L27/108 ,  H01L21/56 ,  H01L21/311 ,  H01L49/02 ,  H01L21/3105 ,  H01L21/027

CPC classification number: H01L27/10894 ,  H01L21/0274 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/565 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/60

Abstract: A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.

公开(公告)号：US12289881B2

公开(公告)日：2025-04-29

申请号：US17948796

申请日：2022-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin Kim ,  Chansic Yoon ,  Hyosub Kim ,  Sohyun Park ,  Junhyeok Ahn

IPC: H10B12/00 ,  H10D64/23

Abstract: Provided is a semiconductor device including a conductive contact plug on a substrate, the conductive contact plug including a lower portion and an upper portion on the lower portion, the lower portion having a first width, and the upper portion having a second width less than the first width, a bit line structure on the conductive contact plug, the bit line structure including a conductive structure and an insulation structure provided in a vertical direction perpendicular to an upper surface of the substrate, and a first lower spacer, a second lower spacer, and a third lower spacer sequentially provided on a sidewall of the lower portion of the conductive contact plug in a horizontal direction parallel to the upper surface of the substrate, wherein an uppermost surface of the third lower spacer is higher than an upper surface of the first lower spacer and an upper surface of the second lower spacer.

公开(公告)号：US20240431097A1

公开(公告)日：2024-12-26

申请号：US18545328

申请日：2023-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjin Lee ,  Jongmin Kim ,  Kiseok Lee ,  Yun Choi ,  Inwoo Kim ,  Hui-Jung Kim ,  Sohyun Park ,  Heejae Chae

IPC: H10B12/00

Abstract: Disclosed is a semiconductor device comprising an active pattern including first and second edge parts spaced apart from each other in a first direction, a word line extending along a second direction between the first and second edge parts, a bit line extending along a third direction on the first edge part, a storage node contact on the second edge part, a first active pad between the bit line and the first edge part, and a second active pad between the storage node contact and the second edge part. The first active pad extends in the third direction more than the first edge part. The second active pad extends in a direction opposite to the third direction more than the second edge part.

公开(公告)号：US20240414909A1

公开(公告)日：2024-12-12

申请号：US18442363

申请日：2024-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyun Park ,  Inwoo Kim ,  Jihun Lee ,  Seongtak Cho

IPC: H10B12/00 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes an active pattern on a substrate; a gate structure extending through an upper portion of the active pattern; a bit line structure on a central portion of the active pattern; a lower contact plug on each of opposite end portions of the active pattern; and an upper contact plug structure on the lower contact plug. The upper contact plug structure includes a first upper contact plug and a second upper contact plug on the first upper contact plug. The second upper contact plug contacts the first upper contact plug. The first upper contact plug includes a first metal pattern and a barrier pattern covering a lower surface and a sidewall of the first metal pattern. An upper surface of the bit line structure contacts a lower surface of the second upper contact plug and does not contact the barrier pattern.

公开(公告)号：US12166903B2

公开(公告)日：2024-12-10

申请号：US17859263

申请日：2022-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungho Lee ,  Sohyun Park ,  Yunho Youm ,  MyungSik Choi

IPC: H04L9/32 ,  G06F21/44 ,  H04L9/30

Abstract: A computing device in a trusted computing (TC) system and an attestation method thereof are provided. The computing device includes at least one processor configured to operate as instructed by program code, the program code including: transmission code configured to cause the at least one processor to transmit, to a master controller, a first identification (ID) for a first device selected among a plurality of devices included in the TC system, a second ID for a second device selected among the plurality of devices, and a nonce; and attestation code configured to cause the at least one processor to perform attestation for the first device and the second device based on an aggregated signature, wherein the aggregated signature is based on generation of a first signature, by the first device, by using the nonce, and generation of a second signature, by the second device, by using the first signature.

公开(公告)号：US20230422488A1

公开(公告)日：2023-12-28

申请号：US18192329

申请日：2023-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin KIM ,  Sohyun Park ,  Chansic Yoon ,  Dongmin Choi ,  Seungbo Ko ,  Hyosub Kim ,  Jingkuk Bae ,  Woojin Jeong ,  Eunkyung Cha ,  Junhyeok Ahn

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/315

Abstract: A semiconductor device including a first contact plug structure on a substrate, a lower spacer structure on a sidewall of the first contact plug structure, and a bit line structure on the first contact plug structure and including a conductive structure and an insulation structure stacked in a vertical direction substantially perpendicular to an upper surface of the substrate may be provided. The first contact plug structure may include a conductive pad contacting the upper surface of the substrate, an ohmic contact pattern on the conductive pad, and a conductive filling pattern on the ohmic contact pattern. The conductive filling pattern may include metal, and include a lower portion having a relatively large width and an upper portion having a relatively small width. The lower spacer structure may contact a sidewall of the conductive filling pattern.

公开(公告)号：US20230189503A1

公开(公告)日：2023-06-15

申请号：US17886652

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyun Park ,  Eunjung Kim

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10888

Abstract: A semiconductor memory device may include a substrate including active regions. Word lines may be on the active regions and may be extended in a first direction. Bit line structures may be on the word lines, and each of the bit line structures may include a contact portion, which is connected to a first impurity region of an active region, and a line portion, which is on the contact portion and which extends in a second direction. Contact plugs may be between the bit line structures and may be connected to respective second impurity regions of the active regions. Connection patterns may connect the contact plugs to the second impurity regions. Each of the connection patterns may include a first concave surface that faces the contact portion and a second convex surface that is opposite to the first surface.

公开(公告)号：US11658117B2

公开(公告)日：2023-05-23

申请号：US17667866

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L29/06 ,  G11C5/10 ,  H01L29/423 ,  H01L27/108 ,  H01L21/768

CPC classification number: H01L23/528 ,  G11C5/10 ,  H01L21/76831 ,  H01L27/10888 ,  H01L29/0649 ,  H01L29/4236

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US20220165657A1

公开(公告)日：2022-05-26

申请号：US17667866

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEJIN PARK ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/528 ,  H01L29/06 ,  G11C5/10 ,  H01L29/423 ,  H01L27/108 ,  H01L21/768

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.