SEMICONDUCTOR LIGHT-EMITTING DEVICES AND SEMICONDUCTOR LIGHT-EMITTING DEVICE PACKAGES
    11.
    发明申请
    SEMICONDUCTOR LIGHT-EMITTING DEVICES AND SEMICONDUCTOR LIGHT-EMITTING DEVICE PACKAGES 审中-公开
    半导体发光器件和半导体发光器件封装

    公开(公告)号:US20160133788A1

    公开(公告)日:2016-05-12

    申请号:US14789278

    申请日:2015-07-01

    CPC classification number: H01L33/20 H01L33/38 H01L33/46 H01L33/54

    Abstract: Semiconductor light-emitting devices, and semiconductor light-emitting packages, include at least one light-emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer sequentially stacked on a substrate, the at least one light-emitting structure having a first region and a second region delimiting the first region. The light-emitting device includes a groove in the second region, and the groove is adjacent to an edge of the substrate and extends parallel to the edge of the substrate.

    Abstract translation: 半导体发光器件和半导体发光封装包括至少一个发光结构,其包括依次堆叠在衬底上的第一导电类型半导体层,有源层和第二导电类型半导体层, 至少一个发光结构具有第一区域和限定第一区域的第二区域。 发光装置包括在第二区域中的凹槽,并且凹槽与衬底的边缘相邻并且平行于衬底的边缘延伸。

    SEMICONDUCTOR MEMORY DEVICE
    12.
    发明申请

    公开(公告)号:US20220157887A1

    公开(公告)日:2022-05-19

    申请号:US17380331

    申请日:2021-07-20

    Abstract: A three-dimensional semiconductor memory device is provided. The semiconductor memory device includes first horizontal conductive lines on a substrate in a first direction, each of the first horizontal conductive lines extending in a second direction different from the first direction, second horizontal conductive lines stacked on the substrate in the first direction, each of the second horizontal conductive lines extending in the second direction, a vertical conductive line between the first horizontal conductive line and the second horizontal conductive line and extending in the first direction, a plurality of first magnetic tunnel junction patterns between the vertical conductive line and each of the first horizontal conductive lines, and a plurality of second magnetic tunnel junction patterns between the vertical conductive lines and each of the second horizontal conductive lines. The first horizontal conductive lines and the second horizontal conductive lines are spaced apart from each other in a third direction.

    SEMICONDUCTOR DEVICE
    13.
    发明申请

    公开(公告)号:US20210036020A1

    公开(公告)日:2021-02-04

    申请号:US16942093

    申请日:2020-07-29

    Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.

    SEMICONDUCTOR DEVICE
    14.
    发明申请

    公开(公告)号:US20200381619A1

    公开(公告)日:2020-12-03

    申请号:US16998542

    申请日:2020-08-20

    Abstract: A semiconductor device includes interlayer insulating layers and horizontal structures alternately and repeatedly disposed on a semiconductor substrate, separation structures extending in a direction perpendicular to an upper surface of the semiconductor substrate on the semiconductor substrate, to extend in a first horizontal direction parallel to the upper surface of the semiconductor substrate, and vertical structures disposed between the separation structures. Each of the horizontal structures includes a plurality of semiconductor regions, and the plurality of semiconductor regions of each of the plurality of semiconductor regions include a first semiconductor region and a second semiconductor region sequentially arranged in a direction away from a side surface of a corresponding one of the vertical structures and having different conductivity types.

    SEMICONDUCTOR DEVICE
    16.
    发明申请

    公开(公告)号:US20180358079A1

    公开(公告)日:2018-12-13

    申请号:US15794628

    申请日:2017-10-26

    CPC classification number: G11C11/40

    Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors, The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.

    SEMICONDUCTOR DEVICE
    17.
    发明公开

    公开(公告)号:US20240047550A1

    公开(公告)日:2024-02-08

    申请号:US18182426

    申请日:2023-03-13

    CPC classification number: H01L29/516 H01L29/41725 H01L29/78391

    Abstract: Provided are semiconductor devices. The semiconductor device includes a substrate, a gate structure disposed on the substrate and extending in a first direction, and an active pattern spaced apart from the substrate in a second direction, extending in a third direction, and penetrating the gate structure, wherein the active pattern includes a two-dimensional material, the gate structure comprises a gate insulating layer, a lower gate conductive layer, a ferroelectric layer, and an upper gate conductive layer, which are sequentially stacked on the active pattern, the gate insulating layer includes hexagonal boron nitride (h-BN), and the ferroelectric layer includes a bilayer of a two-dimensional material.

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