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公开(公告)号：US20240130138A1
公开(公告)日：2024-04-18
申请号：US18483907
申请日：2023-10-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yukio HAYAKAWA , Yong Seok KIM , Bong Yong LEE , Si Yeon CHO
Abstract: A semiconductor memory device includes a cell substrate, a plurality of gate electrodes sequentially stacked on the cell substrate and extending in a first direction, first and second channel structures extending in a second direction different from the first direction and penetrating the plurality of gate electrodes, and a bit line disposed on the plurality of gate electrodes. The first and second channel structures each include a ferroelectric layer, a channel layer, a gate insulating layer and a back gate electrode, which are sequentially disposed on side walls of the plurality of gate electrodes. The first channel structure and the second channel structure are adjacent to each other in the first direction and share a bit line.
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公开(公告)号：US20220139948A1
公开(公告)日：2022-05-05
申请号：US17377848
申请日：2021-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung Hwan LEE , Yong Seok KIM , Il Gweon KIM , Hyun Cheol KIM , Hyeoung Won SEO , Sung Won YOO , Jae Ho HONG
IPC: H01L27/11578 , H01L27/11565
Abstract: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.
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公开(公告)号：US20190019809A1
公开(公告)日：2019-01-17
申请号：US15941978
申请日：2018-03-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyung Hwan LEE , Yong Seok KIM , Tae Hun KIM , Byoung Taek KIM , Jun Hee LIM
IPC: H01L27/11582 , H01L29/423 , H01L29/51 , H01L29/792 , H01L27/11524 , H01L27/11556 , H01L27/11573 , H01L27/11575
Abstract: A vertical memory device and method of manufacture thereof are provided. The vertical memory device includes gate electrode layers stacked on a substrate; a channel layer penetrating through the gate electrode layers; and a first epitaxial layer in contact with a lower portion of the channel layer and including a region having a diameter smaller than an external diameter of the channel layer.
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公开(公告)号：US20180356955A1
公开(公告)日：2018-12-13
申请号：US16104704
申请日：2018-08-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Nam Jo HEO , Sang Yup LEE , Yong Seok KIM , Kwang Sub SON
IPC: G06F3/0488 , G06F3/0481 , G06F3/0484
Abstract: A mobile terminal and a method of supporting an object change for the same are provided. The mobile terminal includes a display unit for outputting at least one object, and a control unit for controlling at least one of directly displaying, in response to a signal for changing the output object into a second object having a similar function but being of a different type than the output object, the second object on the display unit without a screen transition, and for outputting, in response to a signal for changing the output object into a second object having a similar function but being of a different type than the output object, a guide frame on the display unit so as to facilitate change of the output object without a screen transition.
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公开(公告)号：US20240357810A1
公开(公告)日：2024-10-24
申请号：US18757708
申请日：2024-06-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung Hwan LEE , Yong Seok KIM , Il Gweon KIM , Hyun Cheol KIM , Hyeoung Won SEO , Sung Won YOO , Jae Ho HONG
Abstract: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.
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Patent Agency Ranking
公开(公告)号：US20230397443A1
公开(公告)日：2023-12-07
申请号：US18111921
申请日：2023-02-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Min Jun LEE , Yong Seok KIM
CPC classification number: H10B63/845 , H10B63/34 , G11C13/0004 , G11C13/004 , G11C2213/32 , G11C2213/71 , G11C2213/79
Abstract: A resistive memory device includes: a substrate; a plurality of row lines extending in a first direction and spaced apart from each other in a second direction and a third direction, on the substrate, wherein the first direction, the second direction, and the third direction intersect each other; a plurality of column lines extending in the second direction and spaced apart from each other in the first direction, on the substrate; a plurality of upper selection lines extending in the second direction, between the row lines and the column lines; a channel layer extending in the third direction and connected to the plurality of row lines; and a first impurity region and a second impurity region spaced apart from each other in the third direction with the upper selection line interposed therebetween.
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公开(公告)号：US20210249397A1
公开(公告)日：2021-08-12
申请号：US17245299
申请日：2021-04-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kohji KANAMORI , Hyun Mog PARK , Yong Seok KIM , Kyung Hwan LEE , Jun Hee LIM , Jee Hoon HAN
IPC: H01L25/18 , H01L23/00 , H01L27/11556 , H01L27/11582
Abstract: A semiconductor device includes a first semiconductor structure including circuit devices and first bonding pads; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including a base layer; a first memory cell structure including first gate electrodes and first channels penetrating through the first gate electrodes; a second memory cell structure including second gate electrodes and second channels penetrating through the second gate electrodes; bit lines between the first and the second memory cell structures, and electrically connected to the first and second channels in common; first and second conductive layers on the second surface of the base layer; a pad insulating layer having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.
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公开(公告)号：US20210074914A1
公开(公告)日：2021-03-11
申请号：US16592041
申请日：2019-10-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyung Hwan LEE , Yong Seok KIM , Tae Hun KIM , Seok Han PARK , Satoru YAMADA , Jae Ho HONG
Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.
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公开(公告)号：US20190259439A1
公开(公告)日：2019-08-22
申请号：US16405219
申请日：2019-05-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chang Hoon JEON , Yong Seok KIM , Jun Hee LIM
IPC: G11C11/40 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L21/8238 , H01L27/092 , G11C16/04 , H01L21/8234
Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.
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公开(公告)号：US20180374540A1
公开(公告)日：2018-12-27
申请号：US15881208
申请日：2018-01-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sun Gyung HWANG , Byoung Taek KIM , Yong Seok KIM , Ju Seok LEE
Abstract: A memory device includes a memory cell array including a first switch cell, a second switch cell, and a plurality of memory cells disposed between the first the second switch cells and connected to a plurality of word lines, and a control circuit configured to perform a program operation by providing a program voltage to a first word line among the plurality of word lines, a switch voltage to a second word line among the plurality of word lines, and a pass voltage to remaining word lines among the plurality of word lines, wherein the control circuit is configured to turn off the first switch cell and the second switch cell in a first section of the program operation, and configured to turn on the first switch cell and increase the switch voltage in a second section of the program operation later than the first section.
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