公开(公告)号：US20030137048A1

公开(公告)日：2003-07-24

申请号：US10400309

申请日：2003-03-27

Applicant: Staktek Group, L.P.

Inventor： James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly JR. ,  Julian Dowden ,  Jeff Buchle

IPC: H01L023/14

CPC classification number: H05K1/141 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01087 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734

Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.

Abstract translation: 本发明将集成电路堆叠成节省电路板表面积的模块。 在根据本发明的优选实施例设计的两高堆叠或模块中，堆叠一对集成电路，一个集成电路在另一个之上。 两个集成电路与一对柔性电路结构连接。 一对柔性电路结构中的每一个部分地缠绕在模块的下部集成电路的相应的相对侧边缘上。 柔性电路对连接上下集成电路，并且在模块与诸如印刷电路板（PWB）的应用环境之间提供热和电路连接路径。 本发明可以有利于提供用于高密度存储器或高容量计算的模块中的集成电路的多种配置和组合。