公开(公告)号：US11743080B2

公开(公告)日：2023-08-29

申请号：US17083008

申请日：2020-10-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek Manian ,  Amit Rane ,  Ashwin Kottilvalappil Vijayan

IPC: H04L27/01 ,  H04L25/03

CPC classification number: H04L27/01 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885 ,  H04L2025/0349

Abstract: A linear retimer includes an equalizer, a clock recovery circuit, a sample and hold (S/H) circuit, and a linear driver. The equalizer receives an input signal and outputs an equalized signal. The clock recovery circuit receives the equalized signal and outputs a clock signal. The S/H circuit receives the equalized signal and the clock signal and outputs a retimed signal. The linear driver receives the retimed signal and outputs a recovered signal. The S/H circuit is configured to preserve a voltage of the equalized signal in the retimed signal. In some examples, the S/H circuit is part of a linear three-tap feedforward equalizer, and the linear driver receives an output of the feedforward equalizer. The linear retimer can be placed between a transmitter and a channel or after the channel.

公开(公告)号：US20230246884A1

公开(公告)日：2023-08-03

申请号：US17588706

申请日：2022-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek Manian ,  Amit Rane

IPC: H04L25/03 ,  H04B1/16 ,  H03F3/04 ,  H03K17/687

CPC classification number: H04L25/03057 ,  H04B1/16 ,  H03F3/04 ,  H03K17/6872 ,  H03F2200/165

Abstract: Systems, circuitry and methods correct baseline wander while reducing amplitude difference between the input signal to a data sampler and the output signal of an output-swing-controlled buffer. Example baseline wander correction circuitry comprises a baseline wander correction loop that receives an equalized data signal, a feedback signal and a buffer control signal, and corrects baseline wander in the data sampler input signal. Baseline wander correction loop generates the buffer output signal based on the data sampler output signal and the buffer control signal. Baseline wander correction circuitry also comprises a feedback circuit that receives the data sampler output signal and generates the feedback signal, and an amplitude estimation loop that receives the data sampler input and output signals and outputs the buffer control signal to control the peak-to-peak swing of the buffer output signal.

公开(公告)号：US11038723B2

公开(公告)日：2021-06-15

申请号：US16778955

申请日：2020-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amit Rane ,  Charles Michael Campbell ,  Suzanne Mary Vining

IPC: H04L25/03 ,  H04L7/00 ,  G11B20/10

Abstract: At least some aspects of the present disclosure provide for a method. In at least one example, the method includes applying first equalization to a received data signal to generate an equalizer signal and comparing the equalized signal to each of a plurality of reference voltages for a predetermined period of time per respective reference voltage to generate a comparison result. The method further includes determining a plurality of counts with each count of the plurality of counts uniquely corresponding to a number of rising edges in the comparison result for each of the plurality of reference voltages. The method further includes comparing at least one of the plurality of counts to at least another of the plurality of counts to determine a relationship among the plurality of counts and applying second equalization to the received data signal based on the determined relationship among the plurality of counts.

公开(公告)号：US10938385B2

公开(公告)日：2021-03-02

申请号：US16936462

申请日：2020-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Huanzhang Huang ,  Amit Rane

IPC: G06F13/38 ,  H03K17/00 ,  H03K19/003 ,  H03K17/56

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

公开(公告)号：US10749716B2

公开(公告)日：2020-08-18

申请号：US15960532

申请日：2018-04-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dongwei Chen ,  Amit Rane

IPC: H04L25/49 ,  H04L25/03

Abstract: A signal path linearizer for PAM4 SerDes communications compensates (including pre-compensates) for signal path nonlinearities. The linearizer can be configured with first and second differential gm stages, the first differential gm stage to provide a DC gain, and the second differential gm stage to introduce a defined nonlinear adjustment in DC gain by adding to or subtracting from the DC gain of the first differential gm stage. The differential gm stages can be configured to generate a compensated PAM4 signal with the combined DC gain providing a nonlinear wideband gain adjustment to compensate for nonlinearities in the PAM4 signal path. Compensation range can be increased by selective degeneration, and the compensation region can be shifted by selectively introducing input offset(s).